Timing Constraints on the external pins of the chip

[ivlsi]

Hi All,

What considerations should be taking into account while applying Timing Constraints on the External Pins of the Chip? Are there any rules of thumb?

Is it required to define Signal Slops, Transition Time and Load Capacitance?

How to know what I/O pads should be placed (in terms of their strength)?

Thank you!

 

[rca]

If you know the load, the pin will see in your application, for sure add this constraints.
Certain interface protocoles request some max transitions, timing relation from a pad to another pads...
For the strenght choice, the power budget, interface speed, could involve, in functional or test mode, for example, the load on a tester machine is "huge" 100pF, and could required more strengh, to speed-up the test.

 

[ivlsi]

rca, thank you for your comment. How should the PCB routing be taken into consideration? Is there any rule of thumb?