i think you dont need to give any constraints. 3.4 MHz is not a hig speed clock. quartus automatically calculate setup time and hold time for your designs.
I know about xilinx. after place and route, you have to run timing analysis. it gives detailed report about setup time, hold time and slack. probably quartus also does simlarly with different names.
conctrains are needid when you interactiong with other chips on the board, in your case timing constraints for UART portion I would worry because it is low spped, but if on onother side you are interacting with CPU then you will need to assign them.
Also it is depnds if you using TAN it is slightly different approach then if you are using QAN. Altera has appnotes for both also there are tutorials there.