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Timing constraint values for Cylone EP1C6Q240C7 in Quartus II

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yamaha

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Hi all,

I have a working UART code, i need to implement in Cylone EP1C6Q240C7,
Now i have to make it work for 3.6864MHZ.

I need to know what values should i put for

Tsu
Th
Tco
Tpd
in the quartus II software
for 3.6864 MHZ

regards
yam
 

nag123

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Re: Timing Constraint

i think you dont need to give any constraints. 3.4 MHz is not a hig speed clock. quartus automatically calculate setup time and hold time for your designs.
 

    yamaha

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yamaha

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Re: Timing Constraint

Actually i also thought so, but since its not working properly, am having doubts on it,

I wanted to know how one can get estimate values, using the quartus tool,
 

nag123

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Re: Timing Constraint

I know about xilinx. after place and route, you have to run timing analysis. it gives detailed report about setup time, hold time and slack. probably quartus also does simlarly with different names.
 

Iouri

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Timing Constraint

conctrains are needid when you interactiong with other chips on the board, in your case timing constraints for UART portion I would worry because it is low spped, but if on onother side you are interacting with CPU then you will need to assign them.

Also it is depnds if you using TAN it is slightly different approach then if you are using QAN. Altera has appnotes for both also there are tutorials there.

good lack
 

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