Timing Closure in front-end design

[quake]

Timing Closure

Hi. When talk about timing closure in front-end design, usually what kind of techniques do anybody use to reduce path delay?from architechture to gate level.
for eg, when i hope my system run at 500M, but after synthesis is it simply 200M,
what do you do about it since the speed is critical, how about the steps of achieving it?

 

[cedance]

Re: Timing Closure

Hi. When talk about timing closure in front-end design, usually what kind of techniques do anybody use to reduce path delay?from architechture to gate level.
for eg, when i hope my system run at 500M, but after synthesis is it simply 200M,
what do you do about it since the speed is critical, how about the steps of achieving it?

i am not that sure with ur question.. neverhteless to the point i have understood, it is concernec with the routing and placement techniques when u place the devices on the board.. that will reduce the path delay i suppose.. taking an optimised design either for area or power or delay... accordingly would reduce the necessary parameters.. hope i got it right and proved useful..

regards,
arunmit168.

 

[quake]

Re: Timing Closure

Hey, what I mean is to optimize the design at RTL level or obove or below(gates), donn't care about physical design. and also including coding for optimization

 

[eexuke]

Re: Timing Closure

You problem is too generic. There are so many techniques to reduce the cirtical path such as adding more parallel function units,adding more pipeline stages...etc

 

[mark_yeh]

Re: Timing Closure

you use the wrong title "timing clusure". it is not about timing closure, it is about timing performance.

 

[quake]

Re: Timing Closure

You problem is too generic. There are so many techniques to reduce the cirtical path such as adding more parallel function units,adding more pipeline stages...etc

Ok, whatever the topic is, let's talk about these techniques. I should narrow down the problem: when there are feedback logic paths, how can i reduce the delay, since pipelining it wonn't be easy. Sometimes it seems to me the first thing I should do is to add more parallel function units, but the fanout suddenly becomes bigger and the delay from buffers are not acceptable. any other suggestions?

 

[funzero]

Re: Timing Closure

your front-end means after synthesis , you can inspect your code to see if datapath can be pipelined , or your design can only run at 200M.

 

[mst]

Re: Timing Closure

Huge difference in the current frequency after synthesis and your required frequency .......it seems you need to modify your code again .