Timing Budgeting between Blocks

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Hi,
I need to do the following budgeting:

Block 1 --------> AXI Stream Interface --------->Block2

At the moment:
clock Block1 is 500MHz and input/output delays are set to 50%

If I need to increase the clock of Block1, for example to 2GHz, I think that I should change the input/output delay constraints. Am I wrong ? What is the approach that I must follow to prevent setup violation ?

Many thanks,
GDesign
 

Input and Output SDC constrains are used to inform the tool about external interfaces - I.E: the pins of your device. This isn't your case.

Is Block 1 synchronous to Block 2 ?
If not - you'll have to ensure proper clock domain crossing between the 2 (use a dual clock FIFO).
 

Hi,
many thanks for your reply.

Block1 is an external block(macro) that is connected by AXI to Block2.
I am in a very early stage of my design and I would like a method to have a first budgeting.

Sorry for the confusion.
GDesign
 

Yes, Block1 is a macro(ADC, DAC, CPU, etc).
 

GDesign said:
Yes, Block1 is a macro(ADC, DAC, CPU, etc).
Click to expand...

I think you are confused on what budgeting is and where/when it applies. Unless there is a combinational path that starts at block1 and ends at block2, there is no need for budgeting. Just input/output delay modelling.
 

ThisIsNotSam said:
I think you are confused on what budgeting is and where/when it applies. Unless there is a combinational path that starts at block1 and ends at block2, there is no need for budgeting. Just input/output delay modelling.
Click to expand...

Yes, that is what I am asking. My first enquiry was:
"I think that I should change the input/output delay constraints. Am I wrong ?"
 

GDesign said:
Yes, that is what I am asking. My first enquiry was:
"I think that I should change the input/output delay constraints. Am I wrong ?"
Click to expand...

Are you at a company? Please ask a more senior person to explain these concepts to you because you are still asking the wrong questions. The concept of input/output delay is meant to model external interfaces.
 


I think you should change the clock period in the create_clock definition of block1 clock.
 

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