Until CTS done is done, u dont have proper information about clock tree. so u can judge better about Hold violation with Clock network delay information after CTS.
But in the case of Setup, u will have delay information for the data paths, so u can check for setup violation in the Pre-CTS stage.
b4 pre-layout, u have 2 ensure tht ur design is meetin the "specified" operating freq !!!
once ur setup is fixed , then after the RC parasitics values are extracted, u can get accurate delays along with the CT as well , hence hold can be fixed at last !!