Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

TIMING ANALYSIS( SOC ENCOUNTER)

Status
Not open for further replies.

mujju433

Full Member level 3
Joined
Jun 2, 2007
Messages
174
Helped
4
Reputation
8
Reaction score
2
Trophy points
1,298
Activity points
2,293
Why do we check for SETUP at the time of PRE-CTS optimization why not hold?
 

au_sun

Full Member level 2
Joined
Aug 5, 2004
Messages
147
Helped
15
Reputation
30
Reaction score
4
Trophy points
1,298
Activity points
1,184
Until CTS done is done, u dont have proper information about clock tree. so u can judge better about Hold violation with Clock network delay information after CTS.

But in the case of Setup, u will have delay information for the data paths, so u can check for setup violation in the Pre-CTS stage.
 

lakshman.ar

Member level 5
Joined
Nov 29, 2006
Messages
88
Helped
12
Reputation
24
Reaction score
4
Trophy points
1,288
Location
Bangalore
Activity points
1,849
b4 pre-layout, u have 2 ensure tht ur design is meetin the "specified" operating freq !!!

once ur setup is fixed , then after the RC parasitics values are extracted, u can get accurate delays along with the CT as well , hence hold can be fixed at last !!

BR
Lakshman
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top