seanwu
Member level 2
timing analysis
I have generated a DFT ready gate_level netlist, with TestMode connected to "Dummy 0 Clip Cell". When TestMode = 1, the negedge clocked F.F. is changed to posedge clocked F.F., a clock mux is used.
When I analysis timing, PrimeTime knows the F.F. is negedge, but DesignCompiler does not know it, and I must do set_case_analysis to get the correct report_timing results.
Any body who know why ?
I have generated a DFT ready gate_level netlist, with TestMode connected to "Dummy 0 Clip Cell". When TestMode = 1, the negedge clocked F.F. is changed to posedge clocked F.F., a clock mux is used.
When I analysis timing, PrimeTime knows the F.F. is negedge, but DesignCompiler does not know it, and I must do set_case_analysis to get the correct report_timing results.
Any body who know why ?