The critical path analysis indicates with clock element to clock element path contains the longest (in timing point of view) path.
That indicates the maximum speed of the design.
The path could be from input to clock element or clock element to output or input to output.
By clock element, I mean flip-flop, clocked memories..
The false path analysis, I beleive (because I don't call like this), it's to check the SDC doesn't provide unwanted false path. When a path is declare as false path, the timing engine does not take account this path, and then does not check if this one could be the critical or not.
The false path is provide by the SDC to synthesis tool and P&R & STA.
The critical path is analyse along the flow, synthesis-P&R-STA.