Time to Digital Converter

[Jetach]

Hello,

I need some assistance in writing the code for a time to digital converter with high resolution for an FPGA in verilog using delay carries.

I haven't used verilog in a while so any help would be useful.

 

[mrflibble]

1 - this (*) is in my top 3 interests in fpga country
2 - become less vague and I might be able to assist

*) creative perversions in asynchronous logic

 

[Jetach]

1 - this (*) is in my top 3 interests in fpga country
2 - become less vague and I might be able to assist

*) creative perversions in asynchronous logic

As of now I just need a basic TDC to work with, and eventually will try to work on improving the time between the delay chains to make them more uniform/consistent.

But as of now I just need a TDC.

This is to use a ToF for imaging. When the detector notices a signal, it will start the TDC until the next rise of the clock, which would be its stop.

Sorry if I'm not specific enough, please let me know what you would like to know.