Time step in nonblocking assignments

[manjari_eda]

Hi,

I've been trying to understand the nonblocking statements..
I could understand that the evaluation of the RHS happens first followed by the assignment in the LHS in the "next time step"...

Can anyone help me understand what this "next time step" means, I've just started learning verilog and not able to get the next time step assignment meaning....


Thanks and regards,
Manjari

 

[FvM]

The update step of non-blocking assigment without delay specification is executed at the end of the current time step, not in the "next" time step. Review IEEE Std. 1800 Clause 4 and 10 for details.

 

[manjari_eda]

The update step of non-blocking assigment without delay specification is executed at the end of the current time step, not in the "next" time step. Review IEEE Std. 1800 Clause 4 and 10 for details.

Thanks for the pointer... I could now understand that there are different regions maintained by the simulator for each time step.
In the case of nonblocking assignment the evaluation and updation take place in different regions but in the same time step...

Pl let me know if my understanding is right...

Thanks n regards,
Manjari

 

[FvM]

The discrimination of different event queue regions is a matter of exact language specification. For common logic design considerations, it's usually sufficient to know that the LHS of non-blocking assignments is updated at the end of the current time step. That's how things are presented in literature, e.g. the classical cummings paper http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf