Time percentage for write mode in scrubbing

[msdarvishi]

Hello everybody,

If you look at to page 5 of the PDF file "Correcting Single-Event Upsets Through Virtex Partial Configuration (Application Note: XAPP216 (v1.0) June 1, 2000)", in "SEU Scrubbing" section, there was mentioned: "Scrubbing requires substantially less overhead in the system, but does mean that the configuration logic is likely to be in "write mode" for a greater percentage of time." I would like to know how much time percnt would be added for write mode? Can anybody let me know a value? For a survey, I need a specific value if possible. Can anybody assist, please?

Thank you,

 

[dick_freebird]

Presumably you would read continuously (or at some rate which
makes a > 1 bit error an insignificant probability) and only write
back when your EDC shows an error. This in turn would depend
on the upset rate. Upset rate depends on the environment
(orbit, solar activity, shielding) and the device sensitivity.

You can probably find some decent FPGA single event cross-section
curves at NASA NEPP or JPL radiation effects testing web sites.
But you have to assert an environment and the push the cross
section (its Weibull fit coefficients) through a code like CREME
to get a bit error rate. Note that CREME stands a chance of
going unsupported in the near term, and hardly anyone but
rad effects nerds knows how to use or even get at it.

I have paid little attention to FPGAs other than as loads for my
power parts, so this is about all the help I can give you as far
as details. But generally speaking error rates are low, quite low
relative to operating frequencies.

One thing I believe, though, is that config memory is usually
not written -at all- after initial load. So any writing would
certainly raise the write mode percentage (since anything at
all is more than zero). What the operational consequences of
a config-word-write during normal operation might be, I have
no idea.