Time Constraints in Placement

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Dan_Yang

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Hi,
Do we need to set timing constraints at each stage during physical design (from DC compiler to signoff)
If so, how to set timing constraints during placement? (Also source sdc file?)

Looking forward to your kind help, friends!
 

You don't have to do this .. you read the sdc file at the floorplan stage if you readed the .v design, otherwise you can read the ddc file which includes the constraints info of the design.
 
Abdo_Mgdy said:
You don't have to do this .. you read the sdc file at the floorplan stage if you readed the .v design, otherwise you can read the ddc file which includes the constraints info of the design.
Click to expand...

For an inexperienced designer/academic exercise, I would say to load one single SDC and use it all the way. In reality, you will see projects that have different SDCs for different implementation stages. One simple example is to prevent certain cells to be used during logic synthesis but later allow them to be used during physical synthesis. People will also play tricks with estimated/propagated clocks and so on...
 
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