Sunrising
Newbie level 6
tilling ic design
I'd like to know if you do tiling for your analog blocks to meet the metal density rules. If so, how will the filled metal patterns affect the circuit performance and what shall I pay attention to that?
In my opinion, I prefer to no metal filling over the poly gate and diffusion area of the matched devices in a sensitive design. And don't cover the signal wires with metal patterns on both the above and below metals for a signal wire. eg. If a signal wire is on M2, no M1 and M3 metal fillings over it, while M4 and above is OK.
But I'm not sure If I can put metals over the bypass, filter and feedback capacitors' area?
And I'm not sure if we should do LPE and post layout simulation after tiling to characterise the parasitic effect it might caught? If so, how will extraction tool like calibre xRC handle the floating metal patterns?
I'd like to know if you do tiling for your analog blocks to meet the metal density rules. If so, how will the filled metal patterns affect the circuit performance and what shall I pay attention to that?
In my opinion, I prefer to no metal filling over the poly gate and diffusion area of the matched devices in a sensitive design. And don't cover the signal wires with metal patterns on both the above and below metals for a signal wire. eg. If a signal wire is on M2, no M1 and M3 metal fillings over it, while M4 and above is OK.
But I'm not sure If I can put metals over the bypass, filter and feedback capacitors' area?
And I'm not sure if we should do LPE and post layout simulation after tiling to characterise the parasitic effect it might caught? If so, how will extraction tool like calibre xRC handle the floating metal patterns?