Re: On postlayout simulation
Thank you all for the opinions. Here's something to add on my questions.
(1). Some guys working at some analog design companies told me that they usually do not perform the postlayout simulation at all (they're designing power management chips and LCD driver chips). What they said did surprise me and that's why I posted the question here. I do not have much of experience on analog IC, but I think postlayout simulation may be necessary for developing good products.
(2). I have consulted some guys from the manufacturing companies about this question today. They all said that it is quite normal to have the contact of about 20 Ohm with the size of 1um*1um. Although I still think that the parasitic resistance is a little too big, but I accepted it now. And the suggestions from qslazio are very effective, that's what I'm gonna adpot in my design.
(3). I'm using xCalibre to extract my layout, the problem is that the extracted RC are up to several thousands, especially for the VDD and VSS runner. I'm wondering whether it is possible for ADS to "eat" so many device, and give out the right simulation results? (I'm doubting about this, coz the result was OK when I used Hspice to perform the simulation, while ADS gave no results at all )
PS: based on question 3, I'm wondering whether it is necessary or not to extract the parasitic RC for the power lines(VDD and VSS)?? and I wish I could get some advices on this issue, thank you.