Ruritania
Member level 5
On postlayout simulation
Hi, the following two questions open to discussion, thanks.
(1). Is it indispensable to perform postlayout simulation for all of the analog circuits?
(2). I'm now using a 0.8um BiCMOS process to develop an anolog IC. While performing the postlayout simulation, I found that the parasitic of a contact (poly1 to metal1 or poly2 to metal1) is about 20ohm, is this normal? (This is much larger than I supposed)
(3). Is there anyone who has ever used ADS to perform postlayout simulation? I had some problem while importing the Hspice netlist.
Regards.
Hi, the following two questions open to discussion, thanks.
(1). Is it indispensable to perform postlayout simulation for all of the analog circuits?
(2). I'm now using a 0.8um BiCMOS process to develop an anolog IC. While performing the postlayout simulation, I found that the parasitic of a contact (poly1 to metal1 or poly2 to metal1) is about 20ohm, is this normal? (This is much larger than I supposed)
(3). Is there anyone who has ever used ADS to perform postlayout simulation? I had some problem while importing the Hspice netlist.
Regards.