Three Basic Doubts in Verilog......

[Guru59]

1) input i
output o
reg x,y,z

always@(clk)
begin
x <= i ;
y <= x ;
z <= y;
end
assign o = z ;

WHAT IS THE ADVANTAGE OF USING ABOVE FUNCTIONALITY.....?


2) input a,b
output c

c <= a & (| b)

WHAT DOES THE ABOVE OUTPUT...............?


3)input a,b
output c

c <= {a,b}

WHAT DOES THE ABONE OUTPUT...................?





Thanks

 

[no_mad]

Hi Guru59,

The best way to get the answer to all ur Qs and make urself understand is you must do the simulation by urself and check the waveform result.

You can use any verilog simulator to simulate it. If you have a synthesis tool, it is even better. Synthesize the code and see it for urself the gate-netlist.

If you face any problems, you can ask us.

I'm sorry for not giving u any answer to ur Qs. Reason, I want you to put some effort first and this is the best way to learn.

Ok

Regards,
no_mad

 

[sree205]

first : ripple the input thro' 3 flops.
second : if b is a vector, then, its possible to know if 'b' has any of the bit as '1'.
third : concatenated output of a and b.

hope this helps.

 

[anilkumarv]

first one is ripple input. I did not understand the second question. Third answer is the concatenation operation.

 

[hunter694]

1/ This code will generate a datapath in hardware. every clock edge (positive OR negative) will move the data one step through the pipe line x->y->z

2/ This statement will first calculate a bit-wise OR of all the bits in 'b' and then will AND the (single-bit) output of that operation with 'a'

3/ This statement will concatenate the signals 'a' and 'b' into a single signal 'c'

 

[ray123]

normally, (2) and (3) should use blocking assignment instead.

 

[Guru59]

Thanks all for those wonderful replies..............

I was asked in an interview the first question of What is the advantage of using ripple input or Pipeline


Thanks