The "work" entity is Quartus (Lite V18.0)

[monahanz]

I have been using .vhd files from Open Cores with good success in Intel's Quartus.
However in many cases I reach a roadblock. In all such cases there are multiple files to compile.

For example:-
I would like to make a .bdf module from the “Simple UART for FPGA” by Jakub Cabal.

The UART.vhd root file has at the start

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

use IEEE.MATH_REAL.ALL;

all of which are fine with Quartus.


But down a few lines there is:-

os_clk_divider_i : entity work.UART_CLK_DIV

generic map(

DIV_MAX_VAL => OS_CLK_DIV_VAL,

DIV_MARK_POS => OS_CLK_DIV_VAL-1

)

There is a separate file “UART_clk_div.vhl’ in the same directory (which compiles fine BTW).

I get this a lot. Quartus gets hung up on finding the entity “work”

What do I need to add to get Quartus to include files with “work” attached?

Thanks in advance

John

 

[FvM]

It has to be included in the project.

 

[monahanz]

How do I do that?

--- Updated Nov 1, 2021 ---

Never mind I figured out how to do it:-
(Main menu, add/remove files in project)
Thanks so much
John

 

[FvM]

Or in editor window "add current file to project".

 

[TrickyDicky]

"Work" in this context is not an entity, it means "current working library" in vhdl. Usually this will be the library you're compiling the file into.