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the two stage CML output buffer

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chang830

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The output of my circuit is a CML output buffer. I intend to use two stage CML output buffer to get better signal integrity. Can anyone see some disadvantage of it?

Thanks
 

suria3

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The power consumption will be doubled.
 

    chang830

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chang830

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The bandwidth will be affected if cascaded rwo CML ouput buffer?

The adding of another CML stage will introduce another pole and it will decrease the bandwidth, but the rise time of the signal will be more sharp vs. single stage, the bandwidth seemed increased. I have some puzzzle on this contradiction.

Can anyone help to clarify it?
 

suria3

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chang830 said:
The output of my circuit is a CML output buffer. I intend to use two stage CML output buffer to get better signal integrity. Can anyone see some disadvantage of it?

Thanks

Chang,

Pls refer to this paper. It might help you. If you can't find, let me know i will upload for you.

High-Speed Current-Mode Logic Amplifier Using Positive Feedback and
Feed-Forward Source-Follower Techniques for High-Speed CMOS I/O Buffer.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 3, MARCH 2005
 

chang830

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suria3 said:
chang830 said:
The output of my circuit is a CML output buffer. I intend to use two stage CML output buffer to get better signal integrity. Can anyone see some disadvantage of it?

Thanks

Chang,

Pls refer to this paper. It might help you. If you can't find, let me know i will upload for you.

High-Speed Current-Mode Logic Amplifier Using Positive Feedback and
Feed-Forward Source-Follower Techniques for High-Speed CMOS I/O Buffer.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 3, MARCH 2005

Hi suria,
Thanks for the reply. I can not find this paper with google. Would you upload it to me?

Thanks in advance
 

suria3

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chang830 said:
suria3 said:
chang830 said:
The output of my circuit is a CML output buffer. I intend to use two stage CML output buffer to get better signal integrity. Can anyone see some disadvantage of it?

Thanks

Chang,

Pls refer to this paper. It might help you. If you can't find, let me know i will upload for you.

High-Speed Current-Mode Logic Amplifier Using Positive Feedback and
Feed-Forward Source-Follower Techniques for High-Speed CMOS I/O Buffer.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 3, MARCH 2005

Hi suria,
Thanks for the reply. I can not find this paper with google. Would you upload it to me?

Thanks in advance


Chang, here is the paper.
Download at this link. Thx
 

    chang830

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alok_ky

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u need to proper termination network while using CML output buffer.

It will have a high power consumption.
 

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