nemolee
Full Member level 3
Dear Sir,
I think you should meet very often that the timing is changed after we sythesis our RTL code through FPGA sythesis and P & R tools. How do we prevent this condition from happening?
Thanks.
I think you should meet very often that the timing is changed after we sythesis our RTL code through FPGA sythesis and P & R tools. How do we prevent this condition from happening?
Thanks.