Re: Latch based design
Hi sim_333 and all,
As you known, FFs are edge sensitive and Latch are level sensitive. for meet timing circuit, the arrival time of data path must be ready at the input of regsiters (Latch & FFs). that mean arrival time must be less than required time when an clock even (level-sensitive or edge sensitive) happen.
Please load figure into attachment for your knowledge about latch-base design!
In below figure, you can see that a circuit with latch B in the middle of 2 boundary flipflops A & B. Clock period for 2 FFs is 10ns (FF-clock), the driven clock of latch is inverted clock of FF-clock. The data path between FF-A and Latch-B is 7ns (path1) and data path delay between Latch-B and FF-c is 2ns (path2).
If Latch-B is a FF, the path1 data path is too late to be captured by clock-edge even at 5ns (1/2 period). However, because of level-sensitive of latch, the data can be captured when signal-level of latch is still high. => the current state is meet timing, and the next state is also meet timing base on above causing.
You can describe the below figure in another ways, but the latch-base design is very useful for long-path fixing.
Thanks and see you later!