Nov 1, 2006 #1 S steven852 Advanced Member level 4 Joined Apr 24, 2005 Messages 100 Helped 2 Reputation 4 Reaction score 1 Trophy points 1,298 Activity points 2,040 Hi, I have an indexing question in Verilog. For instance, a set of parameters are defined as paramter [7:0] COMM0 = 8'h00, COMM1 = 8'h01, COMM2 = 8'h02, COMM3 = 8'h03, COMM4 = 8'h05, COMM5 = 8'h07; can I later on use COMM[ADDR}? ADDR is a 3-bit input. I guess I can't. If not, what is the simplest way to make such indexing? Thanks
Hi, I have an indexing question in Verilog. For instance, a set of parameters are defined as paramter [7:0] COMM0 = 8'h00, COMM1 = 8'h01, COMM2 = 8'h02, COMM3 = 8'h03, COMM4 = 8'h05, COMM5 = 8'h07; can I later on use COMM[ADDR}? ADDR is a 3-bit input. I guess I can't. If not, what is the simplest way to make such indexing? Thanks
Nov 1, 2006 #2 Q quan228228 Full Member level 4 Joined Mar 23, 2006 Messages 196 Helped 16 Reputation 32 Reaction score 3 Trophy points 1,298 Activity points 2,571 Re: Indexing in Verilog I think you can use "case" statement. for example: case (ADDR) 3'b000: COMM = ...; 3'b001: COMM = ...; ............... default: COMM = ...; endcase I hope this can clear your doubt. David
Re: Indexing in Verilog I think you can use "case" statement. for example: case (ADDR) 3'b000: COMM = ...; 3'b001: COMM = ...; ............... default: COMM = ...; endcase I hope this can clear your doubt. David
Nov 1, 2006 #3 E echo47 Advanced Member level 6 Joined Apr 7, 2002 Messages 3,933 Helped 638 Reputation 1,274 Reaction score 90 Trophy points 1,328 Location USA Activity points 33,176 Re: Indexing in Verilog Correct, you can't write COMM[ADDR] that way. Maybe pass a 64-bit parameter and access it like this (it outputs the eight bytes in sequence): Code: module top (clk, outbyte); parameter [63:0] COMM = 64'h17_13_07_05_03_02_01_00; input clk; reg [2:0] ADDR = 0; output reg [7:0] outbyte; always @ (posedge clk) begin outbyte <= COMM >> (ADDR * 8); ADDR <= ADDR + 1; end endmodule Still ugly though.
Re: Indexing in Verilog Correct, you can't write COMM[ADDR] that way. Maybe pass a 64-bit parameter and access it like this (it outputs the eight bytes in sequence): Code: module top (clk, outbyte); parameter [63:0] COMM = 64'h17_13_07_05_03_02_01_00; input clk; reg [2:0] ADDR = 0; output reg [7:0] outbyte; always @ (posedge clk) begin outbyte <= COMM >> (ADDR * 8); ADDR <= ADDR + 1; end endmodule Still ugly though.
Nov 1, 2006 #4 N nand_gates Advanced Member level 3 Joined Jul 19, 2004 Messages 899 Helped 175 Reputation 350 Reaction score 53 Trophy points 1,308 Activity points 7,037 Re: Indexing in Verilog here is same thing in a little different way! Code: module test(); integer i; parameter npar = 7; parameter wpar = 8; parameter [npar*wpar -1:0] COMM_array = {8'h00, 8'h01, 8'h02, 8'h03, 8'h05, 8'h07, 8'h08}; function [wpar -1 : 0]COMM; input [2:0] index; begin COMM = COMM_array >> (npar - index -1)*wpar; end endfunction initial begin for(i=0; i<7; i=i+1) begin $display("COMM[%0d] = %h",i, COMM(i)); end end endmodule // test
Re: Indexing in Verilog here is same thing in a little different way! Code: module test(); integer i; parameter npar = 7; parameter wpar = 8; parameter [npar*wpar -1:0] COMM_array = {8'h00, 8'h01, 8'h02, 8'h03, 8'h05, 8'h07, 8'h08}; function [wpar -1 : 0]COMM; input [2:0] index; begin COMM = COMM_array >> (npar - index -1)*wpar; end endfunction initial begin for(i=0; i<7; i=i+1) begin $display("COMM[%0d] = %h",i, COMM(i)); end end endmodule // test