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the result of the LVDS has lots of jitter

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frankwen

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how can I avoid them
the
thanks
 

PaloAlto

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You need to drive your output switches with non-overlapping signals

:wink:
 

FvM

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I don't see any "jitter" in the waveform (it may be there, but not visibale in the choosen timescale). You know what jitter means?

As an additional remark, to see meaningful real world waveforms, you may want to load the LVDS driver with some common mode impedance, too.
 

IADanilov

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PaloAlto, can you advise me some papers about driving LVDS output switches with non-overlapping signals?

Does it necessary for design with 2 NMOS and 2 PMOS switches or only for design like in this topic?
 

PaloAlto

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Sorry, I don't have references for that.

It doesn't matter whether they are all NMOS or PMOS and NMOS. The thing is that the current source should never be switched off, so it should never happen that all transistors are off, otherwise you have large peaks in your supplies.

You have to drive that block with signals that overlap at high (If they are all NMOS)
 

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