The question about DC synthesis!

[chenzhao.ee]

The reset signal should be connetted to the AS pin of Flip-flops,but in my designs in which a submodule was instantiated the reset signal is connectted to some combinational logic except these AS pins of Flip-flop.At the first,I thought there must be some problem with this submodule and did a experiment by synthesizing it independently.As a result,the netlist is correct and the reset signal is only connectted to these AS pins of Flip-flop.
How can this result be explained? Please give me some suggestion,tanks!!
Noting: the reset network had been dont_touch_network and ideal_network by command set_dont_touch_network and set_ideal_network!

 

[joe2moon]

The reset signal should be connected to the AS pin of Flip-flops

If this is the design spec, then maybe take a look at the input (for example, RTL code) to the synthesis tool.

Trace fanout of the "reset" signal to make sure it has not been used with other signals.

 

[chenzhao.ee]

I had traced the reset signal and found that all reset signals exited as the following form:
always @(posedge clk or negedge reset)
if (~reset)
(..........)
else
(.........)
According to this ,I am sure that reset signal didn't join in any other data path.But I didn't understand clearly how could DC send out such synthesis result.

 

[sumit_techkgp]

Hi chenzhao.ee,
The problem is not with the tool, it is with your dc script!. U have declared reset signal at the top level and that did not continue because some combinational logic in its path. Declare top level reset as set_false_path -from. This will solve ur problem as per tool is concerned. But there are some other issue!. Now there are some reset which has some combinational logic on that. Because of gate delay u may(i stress this word) have some glitches at the output of generated reset. Flop that generated reset, and re declare reset at the flop output. This is a design issue, and take proper care of it.
Best Regards,
Sumit

 

[shield]

I have also meet similar question.
whether there are some tutorials about the dc systhesis script?

 

[chenzhao.ee]

There are several modules in my design,and the reset signal of each module is generated in the top module by a specific rst generation module.The Flip-flop which generates the reset signal is triggered by the falling edge of clk,and this clk is source clk of the module to which the reset signal would be.

 

[chenzhao.ee]

Thanks for everyone!
After many times experiments ,this problem had been solved.I found that if I had add a command(set_ultra_optimization false)in the synthesis script,the synthesis result would be the sane as our expectation and the reset signal is only connectted to the AS pins of Flip-flops.Through looking up the userguide of DC,I find out that the ultra_optimaztion is enabled by default. So if we want to disable this function of DC ,we must disable it expllicitly in command line.The ultra_optimization function of DC is a powerful about how to optimize the datapath by advanced method and the synthesis result of it is indeed better than DC expert synthesis,but I don't know how can it generate such result and let the reset signal join in the datapath?
Fortunately,we get a right netlist ,although the remain question is still needed to be solved!

Best regards to everyone!

 

[vikas_lakhanpal27]

i went through the whole discussion on this topic and was not able to find wat is the problem if reset is coming in data-path? if it is design specific problem then i dont know but else i am not seeing any probs reset coming in data path. Anyway I think if we should give ultra_optimization to optimize the logic in more good way.
Any comments?

 

[joe2moon]

Way to clarify this issue:
===============
1) Do 'logic equivalence checking'.
If RTL and synthesized Netlist are equivalent.
Then logic synthesis tool does not do anything wrong.

2) If RTL-to-Nelist pass logic equivalence check, then maybe like the following case.

For example, (in RTL code)
reset = (a & b);

And in other block, a signal (in RTL code)
control = (a & b & c);

Then, if logic synthesis tool optimizes at higher effort, then
maybe it will result in (Netlist)
control = reset & c;

So the Net reset appears in other blocks of the synthesized netlist, even 'reset' ONLY exist in always @(posedge clk or negedge reset) in RTL code.