The maximum sampling rate and bit per stage in pipelined ADC

Status
Not open for further replies.
M

m_mosazadeh

Member level 4
Joined
Apr 25, 2004
Messages
69
Helped
0
Reputation
0
Reaction score
1
Trophy points
1,286
Location
iran
Activity points
350
pipelined adc

hi all

what is the maximum achievable sampling rate with piplined adc?

what is the maximum bit per stage in piplined adc?



thanks
 

Re: pipelined adc

such maximum value must be specified at the same time with the resolution. different resolution have different maximum speed achievble.
In CMOS, 8-10bit pipelined ADC fs,max is around 200 MHz.

Maximum bit per stage depends on the typical applications, but usually maximum 3.5b per stage. more bit per stage leads to slower sampling and large power consumption, thus high-speed pipelined usually use 1.5 bit per stage (i.e minimum one)
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…