The maximum sampling rate and bit per stage in pipelined ADC

[m_mosazadeh]

pipelined adc

hi all

what is the maximum achievable sampling rate with piplined adc?

what is the maximum bit per stage in piplined adc?



thanks

 

[terryssw]

Re: pipelined adc

such maximum value must be specified at the same time with the resolution. different resolution have different maximum speed achievble.
In CMOS, 8-10bit pipelined ADC fs,max is around 200 MHz.

Maximum bit per stage depends on the typical applications, but usually maximum 3.5b per stage. more bit per stage leads to slower sampling and large power consumption, thus high-speed pipelined usually use 1.5 bit per stage (i.e minimum one)