Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

the Low Power Methodologies extensively used in the industry

Status
Not open for further replies.

kumar_eee

Advanced Member level 3
Joined
Sep 22, 2004
Messages
814
Helped
139
Reputation
276
Reaction score
113
Trophy points
1,323
Location
Bangalore,India
Activity points
4,677
Low Power Design

What are all the Low Power Methodologies are used in the industry?.

I know there are some methods.
1. Clock Gating
2. Multi-Vt
3. Power Gating.

Which methods is being used extensively these days?.
 

Low Power Design

4. Multi Vdd
5. DVFS

I would say clock gating and multi-vt are used extensively as they require little effort and are relatively simple to implement into the design flow. The other methods require additional effort to the architecture definition, physical design, verification, and/or timing closure.
 

    kumar_eee

    Points: 2
    Helpful Answer Positive Rating
Low Power Design

Hi

Add "operand isolation" too.


tnx
 

Re: Low Power Design

Hi Jimjim2k,

Will you elobarate on "operand isolation". I am first time hearing this.

Regards
 

Re: Low Power Design

Hi,
Operand isolation is similar to clock gating - only this time, we're gating a bunch of logical operations.
A simple example would be a signal going through a bunch of logic (the operation we are targetting to isolate) and leading directly to a MUX input.

We can specify that the Select signal to the MUX & signal goes to an AND gate.
So, if the Select of the MUX chooses a different signal than the first one, the circuit does not have to pass the signal through the operation - the signal has already been stopped at the AND gate.

In the diagram below, the red colour reflects the added component (AND gate) & net used for operand isolation.
 

    kumar_eee

    Points: 2
    Helpful Answer Positive Rating
Are there some tools, which deal with Operand Isolation, or it ALWAYS should be done in the RTL level?
 
Last edited:

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top