low power digital design methodologies

[Durga Srikanth]

Hi every one
I need some materials based on low-power digital design in the nm technology process of CMOS ex(below 90 to 40 nm. below kindly provide material based on low-power design. I really appreciate any help you can provide.

thank you in advance


With regrads
srikanth

 

[dick_freebird]

Using the highest-VT devices for static (or low switching rate)
gates.

Using smaller, lower-VT devices for equal / better IDsat on
very high clock rate gates

In between you'd have to analyze the tradeoff between static
and dynamic power.

Clock gating is a thing now, I gather.

None of this especially specific to geometry, other than that
shorter channels equals more current to care about.

 

[Durga Srikanth]

Using the highest-VT devices for static (or low switching rate)
gates.

Using smaller, lower-VT devices for equal / better IDsat on
very high clock rate gates

In between you'd have to analyze the tradeoff between static
and dynamic power.

Clock gating is a thing now, I gather.

None of this especially specific to geometry, other than that
shorter channels equals more current to care about.

Thank you so much. the leakage current is higher in the short channel process. what are ways to reduce the static leakage? as per the IRTS process from 90 to 40 the power dissipation is getting low but the leakage current keeps on increasing.

 

[dick_freebird]

Are you really up for transistor level customization of libraries?
I kind of don't think so. Been there.

It would be surprising if the target foundry didn't have guidance
on this important topic, which is far from my focus. Who's the
library provider, what do they have to say in their application
docs? You did get those application docs along with all the
other interesting paperwork which you then diligently read (as do
we all), right?

It might behoove you to look closer at where the power (current)
is being spent and why, which could lead you to fix things like
gross oversized repeaters used for lightly loaded clocks and data
bus interfaces but leaking bigly on account of using lvt devices.
Or something. This is where you start engineering for a bit and
hold off on trying to teach the autorouter stupid pet tricks. Only
the one with the design entrails squirming in their hands can read
them. Let alone see the future they foretell. How's the resume,
up to date?

 

[dpaul]

Buy and read any of the bestselling low-power CMOS digital design book.
The search-engine is your friend!

 

[ThisIsNotSam]

Thank you so much. the leakage current is higher in the short channel process. what are ways to reduce the static leakage? as per the IRTS process from 90 to 40 the power dissipation is getting low but the leakage current keeps on increasing.

this trend was true until the introduction of finfets. there is whole new static vs. dynamic power balance these days.

 

[rca]

Major power consumption is not gain during the physical activities but also during the architecture and the RTL coding itself.
The question is so large...