the influence of temperature on ESD circuit?

[samuel]

hello everyone,
I had designed a chip. in the normal temperature, the test of the chips are ok; but after higher temperature(125 ℃) and low temperature(-55 ℃) tests , a problem happens to some of twenty chips , that is, the current of the wrong chips become larger. I had check the wrong chips and found ESD circuit of the vdd pad of the wrong chips have the overflow phenomena.

Why? Anyone can explain this phenomena? thanks.

 

[erikl]

Could it be careless handling during the temperature tests?

 

[dick_freebird]

Thermal stream units can produce static charge (triboelectric?)
if not well grounded. The test floor should have air ionizers and
ESD mats & wrist straps over the place.

But you also need to look at the test program and hardware.
Many tests can put more power into an ESD clamp than it can
take (clamps are sized for the ESD strike, peak current and Joule
energy - never for a continuous overstress in the >mS regime).

If the supply ESD clamp is a complex design, maybe it is leakage-
triggered at high temp and drawing the current it needs to hurt
itself.

A failure analysis to determine whether it is a current-mode or
a voltage-mode failure (see gate ox for breakdown sites, and
then oxide-stripped channel for punchthrough current tracks)
might help you chase the cause.