The following generated clock has no path to its masterclock

[hanchen]

Tool: Design comipler 2008.09 sp1
when i try to compile a very simple code (below):
module test_generated_clock(gclk,grst,out1,out2);
input gclk;
input grst;
output [1:0] out1;
output [1:0] out2;
reg [1:0] out1;
reg [1:0] out2;
wire clk_gen;
always@(posedge gclk or negedge grst)
begin
if (!grst)
out1<=2'b00;
else
out1<=out1+1;
end
assign clk_gen=out1[1];
always@(posedge clk_gen or negedge grst)
begin
if (!grst)
out2<=2'b00;
else
out2<=out2+1;
end
endmodule

I use the below script to compile this code:
source ./synopsys_dc_SMIC18.setup
set DESIGN "test_generated_clock"
read_verilog ./test_generated_clock.v
link

create_clock -period 25 -waveform {0 12.5} [get_ports {gclk}]

set_clock_transition -rise 1 [get_clocks {gclk}]
set_clock_transition -fall 1 [get_clocks {gclk}]
set_clock_uncertainty 2 [get_clocks {gclk}]
set_clock_latency 1 -max [get_clocks {gclk}]

set_dont_touch_network [get_ports {gclk}]
set_dont_touch_network [get_ports {grst}]

set_operating_conditions "slow" -library slow
set_wire_load_model -name "smic18_wl30" -library slow
set_wire_load_mode "enclosed"
set_min_library slow.db -min_version fast.db

change_names -hierarchy -rules BORG
create_generated_clock -name clock_gen -source gclk -divide_by 4 [get_pins out1_reg_1_/Q]

set_dont_touch_network [get_clocks clock_gen]
set_propagated_clock [get_clocks clock_gen]

set_input_delay 10 -clock "gclk" [get_ports {grst}]
set_input_delay 10 -clock "clock_gen" [get_ports {grst}]
set_dont_touch_network gclk

set_output_delay 10 -clock "gclk" [get_ports {out1*}]
set_output_delay 10 -clock "clock_gen" [get_ports {out2*}]

set_load 1 [get_ports {out1*}]
set_load 1 [get_ports {out2*}]

set_fix_hold [get_clocks {gclk}]
set_fix_hold [get_clocks {clock_gen}]


#report_timing -from [get_ports gclk] -to [get_pins out1_reg_1_/Q] -path only
#change_names -hierarchy -rules BORG
#write -f verilog -hierarchy -o ./export/$DESIGN\_netlist.sv

##################
when i run the "check_timing" i run to this warning:
dc_shell> check_timing

Information: Checking generated_clocks...
Warning: The following generated clock has no path to its master clock. (TIM-204)
------------------------------
clock_gen

Information: Checking loops...

Information: Checking no_input_delay...

Information: Checking unconstrained_endpoints...

Information: Checking pulse_clock_cell_type...
1

i man the command "check_timing", but gets few messages.
i try some way to avoid this warning, but i failed.
could anyone tell me why this warning come out ?
and is there any way to avoid this problem?

Thanks!

 

[johanlo]

Re: The following generated clock has no path to its masterc

What I believe is that there exists no timing arcs between the two clocks, hence the warning. I also believe that you should use the create_generated_clock command to make a second clock.

In FPGA you would use a primitive to generate a new clock, and in ASIC you would probably use a oscillator/clock generator.

So to wrap it up, if you want to have two clocks in your design use create_clock and create_generated_clock to be able to time your design.

 

[hanchen]

Re: The following generated clock has no path to its masterc

Thank you for you analysing! but I still have some problems.(I am in ASIC)
why there is no timing arcs from the registers clock pin to its Q pin? After compile, i found that JK FF was used from the netlist. Is it the reason......? Maybe i should try to avoid JK FF in this design in order to find the answer & check the lib file to identify it.

Second, I don't well understand you words "I also believe that you should use the create_generated_clock command to make a second clock".

What I believe is that there exists no timing arcs between the two clocks, hence the warning. I also believe that you should use the create_generated_clock command to make a second clock.

In FPGA you would use a primitive to generate a new clock, and in ASIC you would probably use a oscillator/clock generator.

So to wrap it up, if you want to have two clocks in your design use create_clock and create_generated_clock to be able to time your design.

 

[gharuda]

Re: The following generated clock has no path to its masterc

I believe you are using two clocks 1) gclk
2) grst

from where these clock signal are generated. for eg if your are going to implement the design on a FPGA board, which has a clock circuit called Master clock or on- board clock with certain frequency specified .

So your gclk and grst should be derived from Master clock or on-board clock .
-
By using Clock generate gclk and grst.

 

[hanchen]

Re: The following generated clock has no path to its masterc

Thank you for you suggestion~~
i use signal 'grst' to reset my registers, and gclk is the clock signal of my design.
you mean that the tools(Design comipler) treat the signal 'grst' as a clock?

i understand your words that 'gclk and grst should be derived from Master clock or on-board clock'. But I have been confused that it is relation to my question"The following generated clock has no path to its masterclock".
Because when i compile an signal-clock design, this warning won't come out. This signal clock also should be derived from Master clock or on-board clock.

I think you consider that this warning come out because of the signals grst & gclk have no relation to their master signals.
I read the detail of the warning messages, and i think this warning means that the clk_gen has no path to its master clock gclk. so this is my problem.

Anyway, i will try your sugestion to read what the tools tell.

I believe you are using two clocks 1) gclk
2) grst

from where these clock signal are generated. for eg if your are going to implement the design on a FPGA board, which has a clock circuit called Master clock or on- board clock with certain frequency specified .

So your gclk and grst should be derived from Master clock or on-board clock .
-
By using Clock generate gclk and grst.

 

[gharuda]

Re: The following generated clock has no path to its masterc

I am sorry buddy I didn't get grst to be reset signal (which is similar to clock gclk) just went through your coding first time


but still I didn"t get this part

in your code is clk_gen which is declared to be wire

while in your Dc shell command the constrains are used on clock_gen.which does not appear in the code.

please do clear this part

Added after 8 minutes:





again you created your clock signal

"create_clock -period 25 -waveform {0 12.5} [get_ports {gclk}] "

then what about grst signal, which is a input port,

should we need create a signal by using similar constrain above ?

could you please enlighten me about these issue.

its been a long time i since used DC