Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
If you see in other way around... bottom up approach for a chip means top down for that particular Block/core/submodule right. Thus need to close timing exclusively. Then try and extarct the timing models of the blocks and then perform full chip timing. This will save the run time also.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
