It's not the clock frequency but the edge rate of your signals that you should be worried about in terms of signal integrity effects of vias. The via will have inductance, whose value will depend upon the loop the return current has to pass through to change layers. The via will also have
capacitance in the order of 0.5-1.0pf. If your edge rates are controllable, slow them to least you can get away with in your timing budget If not try and match the number of via's on synchronous signals, try to route on one layer. Decouple your design to provide adeqaute paths to minimise loop inductance.