the depletion device in cmos analog design

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chang830

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Our cmos process provide three FET device types, which are high Vt, low Vt and depletion device.

Can anyone tell me in what conditions the depletion devices used in design? Is any concern(such as mismatch, product yield etc..) in using these devices?

Thanks
 

depletion device is mainly be used as a resistor with Vgs=0.
 

In some I/O circuits, the depletion device is used to improve the driving capacity.
 

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