chang830
Full Member level 5
hi,
My project used 0.5um CMOS process and the design rule gives 90umx90um PAD size recommendations. For area considerations, my pad is decreased to 80Umx80um and the chip will be COB(Chip on board) packaged.
Would any one pls. give me advcie if it have any risks?
Thanks
My project used 0.5um CMOS process and the design rule gives 90umx90um PAD size recommendations. For area considerations, my pad is decreased to 80Umx80um and the chip will be COB(Chip on board) packaged.
Would any one pls. give me advcie if it have any risks?
Thanks