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TFT analog design in Cadence?

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Newbie level 2
Sep 12, 2009
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I'd like to simulate TFT analog circuits using Cadence. I have not been able to find much information about TFT process support in Cadence tools. Does anyone have any experience with this?

Basically, I'd like to see (and implement) the full flow of analog TFT design:

- schematic creation in Virtuoso
- Simulation with Spectre and Ultrasim (using the latest RPI models)
- layout with Virtuoso
- DRC, LVS, ... etc with Virtuoso
- parasitic extraction with Assura
- Back-annotation with Assura
-Post extraction simulation

So far, I've seen brochures outlining this kind of flow in Silvaco's Simucad tools. I haven't found anything similar for Cadence which is my preferred tool set. Any suggestions?


Added after 8 minutes:

This is the info from Silvaco that I was referring to:

**broken link removed**


This sounds more like a PDK access problem, than anything
to do with Cadence. The tools you list are the same ones
I use for everyday IC design. The only thing missing is good
models and rules for TFT process elements.

Thank you for the reply.

I'm working on getting a PDK but that's not what my question is about.

I've been designing ICs in Cadence for more than 10 years. I want to know if I can have the same flow going with TFTs. I have not gotten a clear answer yet!

Theoretically, the answer should be yes. However, I'd to confirm that before committing large sums of money to Cadence.

That's why I'm asking if anyone out there has been successfully running the full analog design flow for TFTs in Cadence tools.

Silvaco seems to have pretty documentation of their flow for TFTs. However, I'd rather use Cadence if I can since I have a lot of experience with it.

If anyone out there knows a good person to contact at Cadence, that'd be welcome too.


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