Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

testing bits in vhdl within if statement

Status
Not open for further replies.

rameshrai

Full Member level 3
Joined
Aug 16, 2010
Messages
159
Helped
7
Reputation
14
Reaction score
7
Trophy points
1,298
Activity points
2,272
Hi,

is there any better way to write the following in vhdl:

Code:
if ((x(0)='0' or x(1)='0' or x(2)='0' or x(3) = '0') and (y(0)='0' or y(1)='0' or y(2)='0' or y(3) = '0')) then

thanks
 

FvM

Super Moderator
Staff member
Joined
Jan 22, 2008
Messages
48,277
Helped
14,226
Reputation
28,713
Reaction score
12,920
Trophy points
1,393
Location
Bochum, Germany
Activity points
279,569
There's nothing bad with the statement. But you can save some writing when
using VHDL2008 logical reduction operators
Code:
if NOT (AND x) AND (OR y) then

or logical reduction functions from syn_misc library

Code:
if nand_reduce(x) AND or_reduce(y) then
 

std_match

Advanced Member level 4
Joined
Jul 9, 2010
Messages
1,187
Helped
444
Reputation
888
Reaction score
409
Trophy points
1,363
Location
Sweden
Activity points
9,162
Why not this:

Code:
if x /= "1111" and y /= "1111" then

It will synthesize to the same logic, but it can be different for simulation with 'X', 'Z' etc.
For vectors with the length specified with a generic, a constant should be used instead of the "1111" vectors:

Code:
constant c_all_ones : std_logic_vector(same range as x and y) := (others => '1');

if x /= c_all_ones and y /= c_all_ones then

This will work without VHDL 2008.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top