testing bits in vhdl within if statement

[rameshrai]

Hi,

is there any better way to write the following in vhdl:

if ((x(0)='0' or x(1)='0' or x(2)='0' or x(3) = '0') and (y(0)='0' or y(1)='0' or y(2)='0' or y(3) = '0')) then

thanks

 

[FvM]

There's nothing bad with the statement. But you can save some writing when
using VHDL2008 logical reduction operators

if NOT (AND x) AND (OR y) then

or logical reduction functions from syn_misc library

if nand_reduce(x) AND or_reduce(y) then

 

[std_match]

Why not this:

if x /= "1111" and y /= "1111" then

It will synthesize to the same logic, but it can be different for simulation with 'X', 'Z' etc.
For vectors with the length specified with a generic, a constant should be used instead of the "1111" vectors:

constant c_all_ones : std_logic_vector(same range as x and y) := (others => '1');

if x /= c_all_ones and y /= c_all_ones then

This will work without VHDL 2008.