testbench problems - outputs cannot obtained

[fanwel]

Dear All,

I'm new in vhdl. I need help for tell me what the false in my code.
Below is my vhdl code where it can simulate successfully in Quartus.
-----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.ALL;

ENTITY haar IS
PORT (
clock : IN bit;
-- Inputs
in1 : IN integer RANGE -127 TO 127;
in2 : IN integer RANGE -127 TO 127;
in3 : IN integer RANGE -127 TO 127;
in4 : IN integer RANGE -127 TO 127;
in5 : IN integer RANGE -127 TO 127;
in6 : IN integer RANGE -127 TO 127;
in7 : IN integer RANGE -127 TO 127;
in8 : IN integer RANGE -127 TO 127;
--Outputs
out1 : OUT integer RANGE -127 TO 127;
out2 : OUT integer RANGE -127 TO 127;
out3 : OUT integer RANGE -127 TO 127;
out4 : OUT integer RANGE -127 TO 127;
out5 : OUT integer RANGE -127 TO 127;
out6 : OUT integer RANGE -127 TO 127;
out7 : OUT integer RANGE -127 TO 127;
out8 : OUT integer RANGE -127 TO 127
);
END haar;

ARCHITECTURE haar OF haar IS
COMPONENT reg
PORT (
input : IN integer RANGE -127 TO 127;
clk : IN bit;
output : OUT integer RANGE -127 TO 127
);
END COMPONENT;

COMPONENT adddiv
PORT (
a : IN integer RANGE -127 TO 127;
b : IN integer RANGE -127 TO 127;
clk : IN bit;
c : OUT integer RANGE -127 TO 127
);
END COMPONENT;

COMPONENT difference
PORT (
a : IN integer RANGE -127 TO 127;
b : IN integer RANGE -127 TO 127;
clk : IN bit;
c : OUT integer RANGE -127 TO 127
);
END COMPONENT;

SIGNAL out_r1, out_r2, out_r3, out_r4, out_r5, out_r6, out_r7,
out_r8, out_r9, out_r10, out_r11, out_r12, out_r13, out_r14,
out_r15, out_r16, out_r17, out_r18, out_r19, out_r20, out_r21,
out_r22, out_r23, out_r24 : integer RANGE -127 TO 127;
SIGNAL out_a1, out_a2, out_a3, out_a4, out_a5, out_a6, out_a7 : integer RANGE -127 TO 127;
SIGNAL out_s1, out_s2, out_s3, out_s4, out_s5, out_s6, out_s7 : integer RANGE -127 TO 127;
SIGNAL clk : bit;

BEGIN
-- Input to Register 1
r1: reg
PORT MAP ( in1, clk, out_r1 );
r2: reg
PORT MAP ( in2, clk, out_r2 );
r3: reg
PORT MAP ( in3, clk, out_r3 );
r4: reg
PORT MAP ( in4, clk, out_r4 );
r5: reg
PORT MAP ( in5, clk, out_r5 );
r6: reg
PORT MAP ( in6, clk, out_r6 );
r7: reg
PORT MAP ( in7, clk, out_r7 );
r8: reg
PORT MAP ( in8, clk, out_r8 );

-- Input to Add_Divide and Difference for stage 1
a1: adddiv
PORT MAP ( out_r1, out_r2, clk, out_a1 );
a2: adddiv
PORT MAP ( out_r3, out_r4, clk, out_a2 );
a3: adddiv
PORT MAP ( out_r5, out_r6, clk, out_a3 );
a4: adddiv
PORT MAP ( out_r7, out_r8, clk, out_a4 );
s1: difference
PORT MAP ( out_r1, out_r2, clk, out_s1 );
s2: difference
PORT MAP ( out_r3, out_r4, clk, out_s2 );
s3: difference
PORT MAP ( out_r5, out_r6, clk, out_s3 );
s4: difference
PORT MAP ( out_r7, out_r8, clk, out_s4 );

--Input to Register 2
r9: reg
PORT MAP ( out_a1, clk, out_r9 );
r10: reg
PORT MAP ( out_a2, clk, out_r10 );
r11: reg
PORT MAP ( out_a3, clk, out_r11 );
r12: reg
PORT MAP ( out_a4, clk, out_r12 );
r13: reg
PORT MAP ( out_s1, clk, out_r13 );
r14: reg
PORT MAP ( out_s2, clk, out_r14 );
r15: reg
PORT MAP ( out_s3, clk, out_r15 );
r16: reg
PORT MAP ( out_s4, clk, out_r16 );

-- Input to AddDiv and Difference for stage 2
a5: adddiv
PORT MAP ( out_r9, out_r10, clk, out_a5 );
a6: adddiv
PORT MAP ( out_r11, out_r12, clk, out_a6 );
s5: difference
PORT MAP ( out_r9, out_r10, clk, out_s5 );
s6: difference
PORT MAP ( out_r11, out_r12, clk, out_s6 );

--Input to Register 3
r17: reg
PORT MAP ( out_a5, clk, out_r17 );
r18: reg
PORT MAP ( out_a6, clk, out_r18 );
r19: reg
PORT MAP ( out_s5, clk, out_r19 );
r20: reg
PORT MAP ( out_s6, clk, out_r20 );
r21: reg
PORT MAP ( out_r13, clk, out_r21 );
r22: reg
PORT MAP ( out_r14, clk, out_r22 );
r23: reg
PORT MAP ( out_r15, clk, out_r23 );
r24: reg
PORT MAP ( out_r16, clk, out_r24 );

--Input to AddDiv and Difference for stage 3
a7: adddiv
PORT MAP ( out_r17, out_r18, clk, out_a7 );
s7: difference
PORT MAP ( out_r17, out_r18, clk, out_s7 );

--Input to Register 4
r25: reg
PORT MAP ( out_a7, clk, out1 );
r26: reg
PORT MAP ( out_s7, clk, out2 );
r27: reg
PORT MAP ( out_r19, clk, out3 );
r28: reg
PORT MAP ( out_r20, clk, out4 );
r29: reg
PORT MAP ( out_r21, clk, out5 );
r30: reg
PORT MAP ( out_r22, clk, out6 );
r31: reg
PORT MAP ( out_r23, clk, out7 );
r32: reg
PORT MAP ( out_r24, clk, out8 );
END haar;
---------------------------------------------------------------------------
The problem is when I make the testbench for the above code, it not generate the outputs. But, the input is correct. Below is my testbench code. Anyone can tell me what I', missing please. Many thanks.
---------------------------------------------------------------------------
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity haar_tb is
end;

architecture bench of haar_tb is

-------------Component Declarations---------------
component haar
PORT (
clock : IN bit;
in1 : IN integer RANGE -127 TO 127;
in2 : IN integer RANGE -127 TO 127;
in3 : IN integer RANGE -127 TO 127;
in4 : IN integer RANGE -127 TO 127;
in5 : IN integer RANGE -127 TO 127;
in6 : IN integer RANGE -127 TO 127;
in7 : IN integer RANGE -127 TO 127;
in8 : IN integer RANGE -127 TO 127;

out1 : OUT integer RANGE -127 TO 127;
out2 : OUT integer RANGE -127 TO 127;
out3 : OUT integer RANGE -127 TO 127;
out4 : OUT integer RANGE -127 TO 127;
out5 : OUT integer RANGE -127 TO 127;
out6 : OUT integer RANGE -127 TO 127;
out7 : OUT integer RANGE -127 TO 127;
out8 : OUT integer RANGE -127 TO 127
);
end component;

--------------Signal Declarations-----------------
signal clock: bit;
signal in1: integer RANGE -127 TO 127;
signal in2: integer RANGE -127 TO 127;
signal in3: integer RANGE -127 TO 127;
signal in4: integer RANGE -127 TO 127;
signal in5: integer RANGE -127 TO 127;
signal in6: integer RANGE -127 TO 127;
signal in7: integer RANGE -127 TO 127;
signal in8: integer RANGE -127 TO 127;
signal out1: integer RANGE -127 TO 127;
signal out2: integer RANGE -127 TO 127;
signal out3: integer RANGE -127 TO 127;
signal out4: integer RANGE -127 TO 127;
signal out5: integer RANGE -127 TO 127;
signal out6: integer RANGE -127 TO 127;
signal out7: integer RANGE -127 TO 127;
signal out8: integer RANGE -127 TO 127 ;
signal input: integer RANGE -127 TO 127;
signal clk: bit;
signal output: integer RANGE -127 TO 127 ;

constant clock_period: time := 10 ns;
signal stop_the_clock: boolean;

begin

---------------Component Instantiation--------------
uut: haar
port map ( clock => clock,
in1 => in1,
in2 => in2,
in3 => in3,
in4 => in4,
in5 => in5,
in6 => in6,
in7 => in7,
in8 => in8,
out1 => out1,
out2 => out2,
out3 => out3,
out4 => out4,
out5 => out5,
out6 => out6,
out7 => out7,
out8 => out8 );

stimulus: process
begin

---------------------First Test------------------
in1 <= 18;
in2 <= 5;
in3 <= 1;
in4 <= 9;
in5 <= 13;
in6 <= 6;
in7 <= 2;
in8 <= 3;
wait for 50ns;
---------------------Second Test------------------
in1 <= 10;
in2 <= 2;
in3 <= 3;
in4 <= 4;
in5 <= 15;
in6 <= 7;
in7 <= 13;
in8 <= 8;
wait for 50ns;
---------------------Third Test--------------------
in1 <= 1;
in2 <= 3;
in3 <= 11;
in4 <= 8;
in5 <= 15;
in6 <= 4;
in7 <= 6;
in8 <= 13;
wait for 50ns;

stop_the_clock <= true;

wait;
end process;

clocking: process
begin
while not stop_the_clock loop
clock <= '1', '0' after clock_period / 2;
wait for clock_period;
end loop;
wait;
end process;
end;

 

[TrickyDicky]

No Idea. Have yo debuged the design to find out where the problem is. You seem to have several layers of heirarchy, some of which we cant see. You need to look at the signals from all levels to see where the problems are occuring.

 

[fanwel]

Dear TrickyDicky,

Why when I simulate haar.vhd code in ModelSim is okay? The outputs obtained is correct. But then, when I make the testbench, the outputs is not obtained.
So, I just want to know, it is my haar.vhd code is correct? Although the testbench code give no outputs.

Many thanks

 

[TrickyDicky]

The Haar.vhd is full of only components. I have no idea what all the components do without their source code.
How did you previously simulate haar.vhd without a testbench?

Post your waveform on this forum.

 

[fanwel]

Dear TrickyDicky,

Actually, all the component's operations have been write into another file, which are;
1) reg.vhd 2) adddiv.vhd 3) difference.vhd
Then, I add all this file including the haar.vhd at ModelSim project and the results is correct.

Many thanks

 

[sanju_]

hi..
--------------Signal Declarations-----------------
signal clk: bit;
this line in test bench is extra??or connected to some thing??

 

[fanwel]

Dear Sanju_,

Actually the code signal clk: bit; is extra code in testbench.

 

[sanju_]

can you show this 1) reg.vhd 2) adddiv.vhd 3) difference.vhd codes?
one more thing did you write test bench?

 

[mm6349]

can you show this 1) reg.vhd 2) adddiv.vhd 3) difference.vhd codes?
one more thing did you write test bench?

>>> when you run ModelSim and simulate the testbench, make sure you select the right module (testbench module) not the UUT (entity). So, you can see the waveforms.


mm

 

[sanju_]

hi mm
i am using only xilinx so i asked him. if he gives code i can run and see where the problem is...

 

[fanwel]

Dear mm and sanju,

Thanks for give response. I has select the testbench module when I run the ModelSim, but the output still cannot obtained.

For sanju, I write the testbench code for reg.vhd, adddiv.vhd and difference.vhd components and run in ModelSim and the results are correct. Know, I try to run for the main code testbench; haar.vhd in ModelSim but I can't.

 

[TrickyDicky]

attach a zip file of your project to this forum.

 

[FvM]

Obtaining no output from the simulation can have different reasons:
- your testbench is not stimulating the design unter test sufficiently
- you don't display the output signals

Typically, it's not a matter of the testbench to display the output signals. You are rather using a list or waveform viewer to display them. You can also visualize the testbench generated signals and check, if they are appropriate.

 

[TrickyDicky]

The problem is because inside haar.vhd, you have created an internal signal called "clk" that is connected to all of the registers. This signal is not connected to anything - the input clock is called "clock".

To solve - delete signal "clk" from inside haar.vhd, and connect all the registers to "clock".

---------- Post added at 09:35 ---------- Previous post was at 09:34 ----------

When I did this - I got outputs.

 

[fanwel]

Dear TrickyDicky,

Okay, I will try it. Thanks for your help.

 

[sanju_]

hi trickydicky
i have one doubt in his tb
is that necessary to declare the reg.vhd, adddiv.vhd and difference.vhd components in test bench ?? only top level is enough right...

 

[TrickyDicky]

yes. You only need to decalre components for instantiations in that file.

You really dont need component declarations at all. You can use direct instantiation:

uut : entity work.haar
port map (
...

This way you dont need two copies of the same thing.

 

[fanwel]

Dear TrickyDicky,

I has remove the "clk" and replace by "clock" for the register component. But, I still can't get the output.
It is I need to replace "clk" to "clock" for all component?

 

[TrickyDicky]

inside haar.vhd - do not modify reg.vhd
you need to replace all "clk" with "clock"

 

[sanju_]

yes. fanwel


mark as solved