Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

testbench for verilog netlist

Status
Not open for further replies.

siva_7517

Full Member level 2
Joined
Jan 16, 2006
Messages
138
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Activity points
2,401
hi all,

Can i use the same testbench for functional simulation in nclaunch and timing verification in gate level simulation (which is already optimized with technology library)
From what i have noticed the model for verilog netlist is different compare to the initial verilog coding(before optimized) because there is standard cell name included in the coding. So must i define the standard cell name in the testbench for gate level simulation?

Siva
 

tarkyss

Full Member level 6
Joined
Aug 1, 2005
Messages
345
Helped
26
Reputation
52
Reaction score
9
Trophy points
1,298
Location
China
Activity points
4,185
you can include your verilog model provided by the library provider in you testbench,
 

siva_7517

Full Member level 2
Joined
Jan 16, 2006
Messages
138
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Activity points
2,401
Hi,

Can i know the command to include the verilog model in the testbench?

siva
 

xuanzhu

Member level 3
Joined
Dec 14, 2002
Messages
64
Helped
5
Reputation
10
Reaction score
1
Trophy points
1,288
Location
shanghai
Activity points
450
if your testbench does not include hierarchy path and internal signal, you can use it directly in your gate lvl simulation. in gate simulation, you need to include your gate library in your gate netlist
 

siva_7517

Full Member level 2
Joined
Jan 16, 2006
Messages
138
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Activity points
2,401
hi,

Is the include command for including the gate library to gate netlist :

'include tools/......./silterra18.v
 

Nandy

Advanced Member level 4
Joined
Dec 16, 2005
Messages
116
Helped
6
Reputation
12
Reaction score
4
Trophy points
1,298
Location
San Jose CA
Activity points
2,399
You can use compile option to include library file.
For example, -v tools/......./silterra18.v in vcs or verilog-xl.

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top