testbench for verilog netlist

[siva_7517]

hi all,

Can i use the same testbench for functional simulation in nclaunch and timing verification in gate level simulation (which is already optimized with technology library)
From what i have noticed the model for verilog netlist is different compare to the initial verilog coding(before optimized) because there is standard cell name included in the coding. So must i define the standard cell name in the testbench for gate level simulation?

Siva

 

[tarkyss]

you can include your verilog model provided by the library provider in you testbench,

 

[siva_7517]

Hi,

Can i know the command to include the verilog model in the testbench?

siva

 

[xuanzhu]

if your testbench does not include hierarchy path and internal signal, you can use it directly in your gate lvl simulation. in gate simulation, you need to include your gate library in your gate netlist

 

[siva_7517]

hi,

Is the include command for including the gate library to gate netlist :

'include tools/......./silterra18.v

 

[tarkyss]

yes

 

[Nandy]

You can use compile option to include library file.
For example, -v tools/......./silterra18.v in vcs or verilog-xl.

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.