test clock requirement - dft compiler

[qjlsy]

Synopsys document said,

For edge-sensitive scan shift style in mixed phases design( posedge and negedge sensitive register co-existing),

" for a positive pulse, the rising-edge-triggered filp-flop must be clocked first; for a negative pulse, the rising-edge-triggered flip-flop must be clocked first."

Why should this rule be met? And what should be done to assure this rule?

Thanks a lot!

 

[dr_dft]

If I understand your question correctly, you are describing requirements of mixing posedge and negedge flip-flops into the same scan chain. The way ATPG works, is it assert a scan input, the pulses the scan clock. So if your scan clock is a positive pulse (0->1->0), the rising edge occurs before falling edge. In this case, you need to posedge flip-flops to be at the end of the scan chain, and the negedge on the head of the chain like this:

scan-in -> NFF1 -> NFF2 -> ... -> NFFn -> PFF1 -> PFF2 -> .. -> PFFm -> scan-out

If you reverse the order (posedge before negedge), you will find that at the boundary, the last posedge and the first negedge flip-flops will alway have the same shifted in value.

Let me know if this is not clear. I can explain it further if you want.

 

[soccer]

can you describe your question more detail?

 

[qjlsy]

Hi, dr_dft, I need you more.

----------------------------------------------------------------------------------------------
scan-in -> NFF1 -> NFF2 -> ... -> NFFn -> PFF1 -> PFF2 -> .. -> PFFm -> scan-out

If you reverse the order (posedge before negedge), you will find that at the boundary, the last posedge and the first negedge flip-flops will alway have the same shifted in value.
----------------------------------------------------------------------------------------------

1. Don't the NFFs' positions and PFFs' positions decide by circuit's function? NFFs and PFFs are just the replacement of non-scanable registers in circuit. So could us modify the path from input pin to output pin?

Whether or not can scan path not follow original functional path? Then what should do in dft synthesis so that scan chain can meet our exception, for example, scan-in -> NFF1 -> NFF2 -> ... -> NFFn -> PFF1 -> PFF2 -> .. -> PFFm -> scan-out

2. Yes, for a positive pulse, PFFs first then NFFs last, this sequence will get same shift in value if there are no other comb logic clouds between these 2 flip-flops.

But it can be ok. It's what I want.

One pluse, 2 registers have same input. If no clock skew occur and timing is ok, why not? Output also can be measured and compared with expected value.

If there are comb logic clouds in the middle, 2 flip-flops may also different value shift in.

All in all, I think it doesn't matter to take any kind of flip-flop sequence. For testing purpose.

Could you give me more help? Thanks a lot!

 

[dr_dft]

qjlsy,

I need to draw more figures to explain this. Give me some time to do this before I get back to you.

 

[dr_dft]

1. Don't the NFFs' positions and PFFs' positions decide by circuit's function? NFFs and PFFs are just the replacement of non-scanable registers in circuit. So could us modify the path from input pin to output pin?

You should not scan re-ordering mix NFFs and PFFs. You can reorder everything within the NFF subchain, and within the PFF subchain, but don't mix NFF and PFF.

Whether or not can scan path not follow original functional path? Then what should do in dft synthesis so that scan chain can meet our exception, for example, scan-in -> NFF1 -> NFF2 -> ... -> NFFn -> PFF1 -> PFF2 -> .. -> PFFm -> scan-out

I believe DFT compiler by default will build separate chains for NFF and PFF, unless you ask it to merge edges. I can't remember the commands to do so.

2. Yes, for a positive pulse, PFFs first then NFFs last, this sequence will get same shift in value if there are no other comb logic clouds between these 2 flip-flops.

But it can be ok. It's what I want.

One pluse, 2 registers have same input. If no clock skew occur and timing is ok, why not? Output also can be measured and compared with expected value.

If there are comb logic clouds in the middle, 2 flip-flops may also different value shift in.

All in all, I think it doesn't matter to take any kind of flip-flop sequence. For testing purpose.

Could you give me more help? Thanks a lot!

Imagine the following scan chain with 2 ffs:
scanin->PFF->NFF->scanout

If my clock is a positive pulse, and I put a 1 on scanin, both PFF and NFF will get 1 after a single clock pulse. Hence we can only have either 00, or 11 pattern.
In the old days, ATPG will not be able to figure out that these 2 flip-flops must be identical. All new ATPG tools can handle this now, including Fastscan and Tetramax, but may cause lower fault coverage if PFF and NFF drive the same cone of logic.
Also, on the shift out side, there is some loss. Imagine the following:
scanin->PFF1->PFF2->NFF->scanout
Let say after the capture cycle, values a, b, and c are captured in PFF1, PFF2, and NFF, respectively. We can observe c right away, since it is connected to scanout. After a rising edge, PFF1 and PFF2 are updated, but NFF does not move, so value of PFF2 is 'a', while NFF is still 'c'. Therefore, 'b' is forever lost, and anything captured by PFF2 will not be observable.
This is why ATPG tools will give you a warning for this kind of violations. It can still create correct patterns, but the fault coverage may suffer a little.