praveenkumardr
Newbie level 4
Can any one write a test bench to test this CIC filter...
basically i'm passing 3 sine waves of frequencies 8 MHz , 16MHz and 24 MHz in 3 separate cases with 80 MHz sine wave being the sampling signal.
I've to take 10 samples , 5 samples and 3.33 samples respectively for each of above cases. below is the excel conversion of a sine wave taking 10 samples at equal duration (i.e 2*pi / 10 = 360 degrees / 10 = 36 degrees duration)... i.e, at 36 degree, 72 degree,108 degree....360 degree.
test bench shall have a text io directive to read 18 bit data input from a text file and to write output to another text file.
using text IO is OK, but i just need a test bench , at least with out text IO directives.
Can any one help ?
decimation factor is 5.
36 0.628318531 0.58778525229247300000 77042.1885884790000 010010110011110010
72 1.256637061 0.95105651629515400000 124656.8797038380000 011110011011110000
108 1.884955592 0.95105651629515400000 124656.8797038380000 011110011011110000
144 2.513274123 0.58778525229247300000 77042.1885884791000 010010110011110010
180 3.141592654 0.00000000000000012251 0.0000000000161 000000000000000000
216 3.769911184 -0.58778525229247300000 -77042.1885884790000 101101001100001110
252 4.398229715 -0.95105651629515400000 -124656.8797038380000 100001100100010000
288 5.026548246 -0.95105651629515400000 -124656.8797038380000 100001100100010000
324 5.654866776 -0.58778525229247300000 -77042.1885884791000 101101001100001110
360 6.283185307 -0.00000000000000024503 -0.0000000000321 000000000000000000
-- Module Name: cic.vhd
-- Target Devices: XC6VSX315t-1ff1156
-- Tool versions: ISE 12.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity cic is
generic(CI_SIZE : integer := 18; -- cic input data width
CO_SIZE : integer := 30; -- cic output data width
STAGES : integer := 5);
ce : in std_logic; -- clock enableport (clk : in std_logic; -- system clock (80 Mhz)
ce_r : in std_logic; -- decimated clock by factor of 5 used in comb section
rst : in std_logic; -- system reset
d : in std_logic_vector (CI_SIZE-1 downto 0); --input data
q : out std_logic_vector (CO_SIZE-1 downto 0)); --output data
end cic;
architecture syn of cic is
-- array definition for integrator and comb section
type d_array_type is array (STAGES downto 0) of std_logic_vector(CO_SIZE-1 downto 0);
-- array definition for comb section
type array_type is array (STAGES downto 1) of std_logic_vector(CO_SIZE-1 downto 0);
signal d_fs : d_array_type;
-- used in the integrator section
signal d_fsr : d_array_type;
-- used in the differentiator section, at rate r
signal m1 : array_type;
-- used in the differentiator section, at rate r
signal id : std_logic_vector(CO_SIZE-1 downto 0):= (others =>'0');
-- to use for sign extended version of the input
begin
-- output data
q <= d_fsr(STAGES);
-- input data (d input is sign extended to 30 bits)
id(CO_SIZE-1 downto CI_SIZE) <= (others => d(CI_SIZE-1));
id(CI_SIZE-1 downto 0) <= d;
-- integrator section
process(clk)
begin
if(clk'event and clk = '1') then
if(rst = '1') then
d_fs(0) <= (others => '0');
for i in 1 to STAGES loop
d_fs(i) <= (others => '0');
end loop;
elsif(ce = '1') then
d_fs(0) <= id;
for i in 1 to STAGES loop
d_fs(i) <= d_fs(i-1) + d_fs(i);
end loop;
end if;
end if;
end process;
-- differentiator (comb) section
process(clk)
begin
if(clk'event and clk = '1') then
if(rst = '1') then
d_fsr(0) <= (others => '0');
for i in 1 to STAGES loop
m1(i) <= (others => '0');
d_fsr(i) <= (others => '0');
end loop;
elsif(ce = '1') then
d_fsr(0) <= d_fs(STAGES);
if (ce_r = '1') then
for i in 1 to STAGES loop
m1(i) <= d_fsr(i-1);
d_fsr(i) <= d_fsr(i-1) - m1(i);
end loop;
else
m1 <= m1;
for i in 1 to STAGES loop
d_fsr(i) <= d_fsr(i);
end loop;
end if;
end if;
end if;
end process;
end syn;
basically i'm passing 3 sine waves of frequencies 8 MHz , 16MHz and 24 MHz in 3 separate cases with 80 MHz sine wave being the sampling signal.
I've to take 10 samples , 5 samples and 3.33 samples respectively for each of above cases. below is the excel conversion of a sine wave taking 10 samples at equal duration (i.e 2*pi / 10 = 360 degrees / 10 = 36 degrees duration)... i.e, at 36 degree, 72 degree,108 degree....360 degree.
test bench shall have a text io directive to read 18 bit data input from a text file and to write output to another text file.
using text IO is OK, but i just need a test bench , at least with out text IO directives.
Can any one help ?
decimation factor is 5.
36 0.628318531 0.58778525229247300000 77042.1885884790000 010010110011110010
72 1.256637061 0.95105651629515400000 124656.8797038380000 011110011011110000
108 1.884955592 0.95105651629515400000 124656.8797038380000 011110011011110000
144 2.513274123 0.58778525229247300000 77042.1885884791000 010010110011110010
180 3.141592654 0.00000000000000012251 0.0000000000161 000000000000000000
216 3.769911184 -0.58778525229247300000 -77042.1885884790000 101101001100001110
252 4.398229715 -0.95105651629515400000 -124656.8797038380000 100001100100010000
288 5.026548246 -0.95105651629515400000 -124656.8797038380000 100001100100010000
324 5.654866776 -0.58778525229247300000 -77042.1885884791000 101101001100001110
360 6.283185307 -0.00000000000000024503 -0.0000000000321 000000000000000000
-- Module Name: cic.vhd
-- Target Devices: XC6VSX315t-1ff1156
-- Tool versions: ISE 12.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity cic is
generic(CI_SIZE : integer := 18; -- cic input data width
CO_SIZE : integer := 30; -- cic output data width
STAGES : integer := 5);
ce : in std_logic; -- clock enableport (clk : in std_logic; -- system clock (80 Mhz)
ce_r : in std_logic; -- decimated clock by factor of 5 used in comb section
rst : in std_logic; -- system reset
d : in std_logic_vector (CI_SIZE-1 downto 0); --input data
q : out std_logic_vector (CO_SIZE-1 downto 0)); --output data
end cic;
architecture syn of cic is
-- array definition for integrator and comb section
type d_array_type is array (STAGES downto 0) of std_logic_vector(CO_SIZE-1 downto 0);
-- array definition for comb section
type array_type is array (STAGES downto 1) of std_logic_vector(CO_SIZE-1 downto 0);
signal d_fs : d_array_type;
-- used in the integrator section
signal d_fsr : d_array_type;
-- used in the differentiator section, at rate r
signal m1 : array_type;
-- used in the differentiator section, at rate r
signal id : std_logic_vector(CO_SIZE-1 downto 0):= (others =>'0');
-- to use for sign extended version of the input
begin
-- output data
q <= d_fsr(STAGES);
-- input data (d input is sign extended to 30 bits)
id(CO_SIZE-1 downto CI_SIZE) <= (others => d(CI_SIZE-1));
id(CI_SIZE-1 downto 0) <= d;
-- integrator section
process(clk)
begin
if(clk'event and clk = '1') then
if(rst = '1') then
d_fs(0) <= (others => '0');
for i in 1 to STAGES loop
d_fs(i) <= (others => '0');
end loop;
elsif(ce = '1') then
d_fs(0) <= id;
for i in 1 to STAGES loop
d_fs(i) <= d_fs(i-1) + d_fs(i);
end loop;
end if;
end if;
end process;
-- differentiator (comb) section
process(clk)
begin
if(clk'event and clk = '1') then
if(rst = '1') then
d_fsr(0) <= (others => '0');
for i in 1 to STAGES loop
m1(i) <= (others => '0');
d_fsr(i) <= (others => '0');
end loop;
elsif(ce = '1') then
d_fsr(0) <= d_fs(STAGES);
if (ce_r = '1') then
for i in 1 to STAGES loop
m1(i) <= d_fsr(i-1);
d_fsr(i) <= d_fsr(i-1) - m1(i);
end loop;
else
m1 <= m1;
for i in 1 to STAGES loop
d_fsr(i) <= d_fsr(i);
end loop;
end if;
end if;
end if;
end process;
end syn;