B21hasni
Junior Member level 3
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(
a : in std_logic_vector (15 downto 0);
b : in std_logic_vector (15 downto 0);
s : out std_logic_vector (15 downto 0);
cf : out std_logic;
ovf : out std_logic
);
end adder;
architecture adder of adder is
begin
process (a,b)
variable temp: std_logic_vector (16 downto 0);
begin
temp := ('0'& a) + ('0'& b);
s<= temp(15 downto 0);
cf<= temp(16);
ovf<= temp(15) xor a(15) xor b(15) xor temp (16);
end process;
end adder;
How can Iwrite a test bench for the above design?