Test bench for a recursive function

Dear Folks

I am looking to understand the code in following link. Also, I want to write a test bench so that I can see the result. i can write the test bench for normal clock, counter etc but i neva face a function.

The link is

VHDL coding tips and tricks: Recursive functions in VHDL

I will appreciate for your help

Thanks

regards

Bloke203

Where's the problem. Set an input vector and get the output.

I didn't yet find applications for VHDL function recursion, in the present case, a simple loop does the same.

hello FvM

Thanks for your quick reply. I try to write the test bench as

------------------------------------------------------

library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;

-- Add your library and packages declaration here ...

entity recursion_tb is
end recursion_tb;

architecture TB_ARCHITECTURE of recursion_tb is
-- Component declaration of the tested unit
component recursion
port(
num : in STD_LOGIC_VECTOR(15 downto 0);
exor_out : out STD_LOGIC_VECTOR(1 downto 0) );
end component;

-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal num : STD_LOGIC_VECTOR(15 downto 0):= "1111001100010101";
-- Observed signals - signals mapped to the output ports of tested entity
signal exor_out : STD_LOGIC_VECTOR(1 downto 0);
-- function exor( );

-- Add your code here ...

begin

-- Unit Under Test port map
UUT : recursion
port map (
num => num,
exor_out => exor_out
);

-- Add your stimulus here ...

--signal num <= "1111001100010101";

-- exor_out <= exor(num);

exor_out <= exor_out;

end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_recursion of recursion_tb is
for TB_ARCHITECTURE
for UUT : recursion
use entity work.recursion(behavioral);
end for;
end for;
end TESTBENCH_FOR_recursion;

------------------------------------------------------------


Can you point out how should i have to write as the above does not generate the output?

Thanks

Regards

Bloke 203

No, I would expect the simulation to work. But you can look inside the dut, how the input stimlus is propagated.

This line is wrong, however:
exor_out <= exor_out;

I tried again as

----------------------------------------------

library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;

entity recursion_tb is
end recursion_tb;

architecture TB_ARCHITECTURE of recursion_tb is

component recursion
port(
num : in STD_LOGIC_VECTOR(15 downto 0);
exor_out : out STD_LOGIC_VECTOR(1 downto 0) );
end component;

signal num : STD_LOGIC_VECTOR(15 downto 0):= "1111001100010101";

signal exor_out : STD_LOGIC_VECTOR(1 downto 0);


begin

UUT : recursion
port map (
num => num,
exor_out => exor_out
);

end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_recursion of recursion_tb is
for TB_ARCHITECTURE
for UUT : recursion
use entity work.recursion(behavioral);
end for;
end for;
end TESTBENCH_FOR_recursion;

-----------------------------------------------------------------------------------


https://obrazki.elektroda.pl/98_1293895657.jpg

or



---------- Post added at 17:28 ---------- Previous post was at 17:27 ----------

Nothing appears at exor_out.......

can you help me FvM?