Circuit "best practices" have changed continually since
the first IC (although there is a long tail that survives).
Processes have changed even more so, and drag the
circuit design art along. You can't do the same things
with a 40V bipolar technology as you can with a 1.0V
CMOS. You can't even do the same things with 1.0V
as you could with 5V CMOS - not enough headroom to
cascode everything (and your Rout got way, way
worse as did your Early voltage relative to supply span).
Autozero supplants t=0 trimmed resistors. Sampled
replaces continuous-time (because today the info is
destined to be digitized at some point, so why not
where it provides accuracy advantage as well?).
I doubt it's true that -every- node drives circuit design
changes. I didn't see that when we went from "40V"
to a brief flirtation with 20V bipolar. Not much change
from 5V to 3.3V CMOS. But low level device realities
are probably going to "show you some stuff" between
(say) 1.2V JI CMOS, and 0.6V FinFET (or whatever FinFETs
like for lunch). As voltages drop, you run into noise which
does not, but wants schemes that fold, shape, sample
it away (uV noise means less to a +/-10V system than
a +/-500mV system, especially as word-width and the
overall effective accuracy expectation moves ever higher).