technology node and channel length

[ranger01]

Yeah I did try to search the forum for my question but never got a satisfactory answer., So here's my question...
What is the difference between a technology node and the channel length? Can anyone explain this with an example of 90nm technology node.,?

 

[Kuxx]

Hi ranger01,

there is no difference, technology node is the channel length of typical standard core-voltage transistor for current technology.

Best regards,
Kuxx.

 

[saurabhr8here]

Hi ranger01,

there is no difference, technology node is the channel length of typical standard core-voltage transistor for current technology.

Actually, this used to be true for earlier technology nodes (0.25um/0.18um). There is a source/drain overlap region under the channel, leading to Leff = Ldrawn - Loverlap. Hence, Leff used to be quite a bit less than the actual drawn length. For example, a 0.25um drawn length would have an Leff ~ 0.2um or so. However, to get more benefit of scaling, Intel has scaled their length more aggressively, for example, the transistor channel length for 65nm node was closer to 40nm. However, recently channel length scaling has pretty much come to a halt, for example, a 22nm node DOES NOT have a 22nm channel. The length is more like 30 or 34nm (Check out Intel's IEDM 2012 paper on their 22nm SoC process). The reason being short channel effects (Sub Vt slope and DIBL) are so bad below 25nm, no foundry is really scaling the transistor length any more, at least not by the technology node name value. They are moving to FinFETs which give them better electrostatics and higher drive current due to the 3D fin height. They do scale the contacted poly pitch and M1 pitch which gives them area scaling, but the transistor channel length scaling has slowed down a LOT since the 65/45nm nodes.

Check out slide 5 onwards in this presentation for more information: https://microlab.berkeley.edu/text/seminars/slides/moroz.pdf.

To summarize and answer the original question, technology node names were traditionally based on the actual channel length, now they are continued by Intel/foundries assuming a 0.7X scaling value (90*0.7 ~ 65, 65*0.7 ~ 45). The actual channel length varies a lot depending on the foundry, fabrication technology. Before the 32nm node, the transistor lengths were SMALLER than the drawn length or technology node name. Now they are LARGER than the technology node name. Performance gain due to length scaling has stopped and is actually worse due to bad electrostatics. Moving on, to 20 and 14nm nodes, the channel length will be much larger. Now the node names denote the 'possible' gain in area by scaling the metal 1 pitch (vertical scaling by 0.7X) and contacted gate pitch (horizontal scaling by 0.7X) to give a total of 0.5X scaling, though this is in trouble as well due to lithography constraints.

Hope this helps.

Regards

 

[ranger01]

Hi saurabhr8here,

thank you very much for the reply. Now I understand the difference between technology node and channel length. But are you saying that below 32nm the channel length remains constant (at a LARGER value than the node), irrespective of the node ?

 

[saurabhr8here]

In short, yes the channel length does not scale by the value of the 'technology node'. Please take a look at Intel's 2012 IEDM paper where they mention that the transistor channel lengths of their 22nm FinFET node is 30nm or larger (depending on the Vt of the transistor).

Area scaling comes from two different values:

1. The metal pitch scaling or MP (determines the height of standard cells for large synthesis based designs)
2. Gate pitch GP(Minimum space between the gate regions).

Hence the area of your design ( or standard cells) scales by MPxGP, assuming your standard cell height does not change from one generation to another. If you can fit your device (channel+source+drain) in one gate pitch, it doesn't matter what exact gate length you have. As I mentioned in the previous post, at 45/65nm node and earlier, foundries went for very aggressive channel length scaling. Now its nearly constant, close to 25~30nm. Moving on, I am sure they'd try to scale channel length but for any semiconductor technology, scaling beyond 20nm transistor length would be extremely difficult.

To improve performance from node to node, channel strain engineering is used where mobility of the devices improve and gives higher drive current. In fact PMOS drive strength is nearly equal to NMOS drive strength in recent technologies because PMOS responds more favorably to strain then NMOS.