Technique to speed up full chip simulation?

[bicave]

You know full chip simulation need longtime. Which technique do you often you to speed up?

 

[wangyufn]

-simulation options to reduce the accuracy
-verilog A for behaviour model
-netlist reduction and simplification
......

 

[walker5678]

and set initial condition...

 

[alinalin19832007]

VHDL-AMS models