Jan 9, 2009 #1 B bicave Full Member level 1 Joined Jun 19, 2006 Messages 97 Helped 4 Reputation 8 Reaction score 2 Trophy points 1,288 Activity points 1,910 You know full chip simulation need longtime. Which technique do you often you to speed up?
Jan 10, 2009 #2 W wangyufn Junior Member level 3 Joined Jul 29, 2005 Messages 29 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location Shanghai, China Activity points 1,507 -simulation options to reduce the accuracy -verilog A for behaviour model -netlist reduction and simplification ......
-simulation options to reduce the accuracy -verilog A for behaviour model -netlist reduction and simplification ......
Jan 12, 2009 #3 W walker5678 Full Member level 3 Joined May 17, 2006 Messages 179 Helped 7 Reputation 14 Reaction score 3 Trophy points 1,298 Activity points 2,493 and set initial condition...
Jan 12, 2009 #4 A alinalin19832007 Newbie level 5 Joined Oct 16, 2008 Messages 9 Helped 3 Reputation 6 Reaction score 0 Trophy points 1,281 Activity points 1,324 VHDL-AMS models