Here, as I have understood you want to do functional verification of a design. For this you need to manually write a good test-bench using a HDL.I tried to write testbench but the design i am testing is very big and not fully known to me. So i was told to test few new functionality.
How would typing TCL into a command line ever be more convenient than typing into an HDL model? Regardless of design size, using TCL would probably only be better if you're fluent in TCL and an HDL throwback.This approach works fine and is very convenient if you are testing a small design. For big designs like the ones which you are testing, it is not a good idea. Using HDL is a better approach.
How would typing TCL into a command line ever be more convenient than typing into an HDL model? Regardless of design size, using TCL would probably only be better if you're fluent in TCL and an HDL throwback.
Kevin
I think both are ways to simulate your design. Difference is of either writing HDL testbench or providing TCL scripts. Correct me if i am wrong.In the 2nd paragraph, what you have mention is design simu automation work. I hope you understand that both are completely different things.
You are correct Kevin its not a convenient and i am not fluent in TCL but i am trying and you can help me.How would typing TCL into a command line ever be more convenient than typing into an HDL model? Regardless of design size, using TCL would probably only be better if you're fluent in TCL and an HDL throwback.
I am not doing it via (.do) file because i am not sure how to do so. I have located (.vho) file in my project folder and simply run via double clicking. There i have command line interface of ModelSim where i paste TCL commands return in some different (.txt) file. And input/output signals can be observed over WAVE window.Well, you can type it first and then copy them into a .do file and then run the .do file.....For a big design you will have to type a lot of commands. Not so for a small design..
In addition to the .VHO file, you should also have the original source .VHD file. Get the testbench working with that first. Then substitute in the .VHO file. Both will have the same interface with the testbench so no changes should be needed to get the testbench working other than to fix issues with the testbench itself.The correct way is to write an HDL twstbench, but i am bound to use the same my project where i have VHDL Output File (.vho) available with me. Extension vho is a output of Quartus(Altera) simulator tool for FPGA. And only tcl is the way i find to test the design. Now i am in some progress with this but i still need to capture that value from data bus which is of output net type. Any suggestion ??
I think both are ways to simulate your design. Difference is of either writing HDL testbench or providing TCL scripts. Correct me if i am wrong.
Thanks Tricky (.do) file is easy to handle. I am using the same for my TCL for now.:thumbsup:do myfile.do to execute the script, rather than copy/pasting each command manually.
Hello Kevin i am getting your point but i dont have orignal source code. That's the reason i am using TCL to varify the design, so i am trying to dump data bus output in a text file then observe the sequence and verify the design 8-OIn addition to the .VHO file, you should also have the original source .VHD file. Get the testbench working with that first. Then substitute in the .VHO file. Both will have the same interface with the testbench so no changes should be needed to get the testbench working other than to fix issues with the testbench itself.
There is nothing to do to capture the outputs, they are already there. What you would do is check to see that they are correct with an assertion statement.
Hello PaulNow lets take a step backward. Do you have a testbench, a .vhd file with which you can provide stimulus to your DUT and can simulate your design (run for some us and see waveforms, etc)?
If yes, good, you have step-1 done. The next step would be the process of automatically running your testbench. That is done using a TCL script which will contain successive TCL commands bundled in a .do file. We can keep this aside currently; subjected to future discussion.
If not, then please develop a running test-bench first. TrickyDicky & K-J have already told you to do this in the last two posts. This is the first thing you must do.
I understand that simulating a big DUT repeatedly gets annoying over time and hence you want a TCL script to it. Yes, right approach. But I think the members (including me) are not sure if have a running test-bench!
Even if you don't have source code you can still write a testbench based on the interface specs. I'm not sure why you have a problem with that and insist on using a Tcl script to toggle the inputs of the DUT.Hello Kevin i am getting your point but i dont have orignal source code. That's the reason i am using TCL to varify the design
1-step is the basics approach that i always follow, when i have source code written in HDL(Verilog or VHDL). But in this recent project, i don't have source code. Just the VHDL Output File (.vho) and few snapshots of block diagram.
Writing a testbench is not a problem. The problem is instantiating the top level in my testbench and then compile it. It can be easily done when i have source code but i don't know how to include my top_level_design which is already been compiled separately and i am left with VHDL Output File (.vho)Even if you don't have source code you can still write a testbench based on the interface specs. I'm not sure why you have a problem with that and insist on using a Tcl script to toggle the inputs of the DUT.
The .VHO file is VHDL source, you just compile it. Probably what you'll find is that you need to include various other device specific packages as well. These will be identified though as errors about unrecognized identifiers when you compile the .VHO file. So then you search the tool's directory to find the other files you need, compile them, compile the VHO file again. Repeat this process until the VHO file compiles without error.Writing a testbench is not a problem. The problem is instantiating the top level in my testbench and then compile it. It can be easily done when i have source code but i don't know how to include my top_level_design which is already been compiled separately and i am left with VHDL Output File (.vho)
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