[SOLVED] TCL testbench in Modelsim

[prady019]

I have seen some threads about people seeking help in TCL scripts when you simulate a design on ModelSim without a testbench and i am one of them. I tried to write testbench but the design i am testing is very big and not fully known to me. So i was told to test few new functionality. :bang: :bang: :bang: :bang:

I took some advise from threads and read the application note for the same and modelsim_commands.pdf attached below.
Steps i follow are as follow
1. Create a project
2. Add all the .vhd files of design and compile them all.
3. Start the simulation via gui.
4. Transcript is available to write tcl scripts.

Few commands that helped me out starting simulation are
add wave
force -freeze
run
noforce


Combining these commands you can start your simulation and observe waveform in wave window. I have come this far and need your help guys. The problem i am facing is 'When i run the design after applying all the valid input to my DUT i can see change on my output net/reg. I have to read each value and then have to check whether its correct. Now i need to transfer the value in a TCL variable which i can use further to dump in a file or to apply some formula on that values to check where the output are correct or not.'

 

[TrickyDicky]

Driving a simulation like that sounds like a terrible idea. Why don't you just do the same from hdl. Then you have direct access to the outputs so your can easily output to a text file.

I have never seen anyone test a module the way you describe

 

[sharath666]

This approach works fine and is very convenient if you are testing a small design. For big designs like the ones which you are testing, it is not a good idea. Using HDL is a better approach.

 

[dpaul]

I am not sure what you actually want.

I tried to write testbench but the design i am testing is very big and not fully known to me. So i was told to test few new functionality.

Here, as I have understood you want to do functional verification of a design. For this you need to manually write a good test-bench using a HDL.

In the 2nd paragraph, what you have mention is design simu automation work.

I hope you understand that both are completely different things.

My advice to you would be to separate out the above two tasks and handle one at a time. First develop the requisite test-bench and initially you can manually run the sims using the commands.
Later when are sure which signals you have include in the waveform window, how long to run the sims, go for a TCL script.

 

[K-J]

This approach works fine and is very convenient if you are testing a small design. For big designs like the ones which you are testing, it is not a good idea. Using HDL is a better approach.

How would typing TCL into a command line ever be more convenient than typing into an HDL model? Regardless of design size, using TCL would probably only be better if you're fluent in TCL and an HDL throwback.
Kevin

 

[sharath666]

How would typing TCL into a command line ever be more convenient than typing into an HDL model? Regardless of design size, using TCL would probably only be better if you're fluent in TCL and an HDL throwback.
Kevin

Well, you can type it first and then copy them into a .do file and then run the .do file.....For a big design you will have to type a lot of commands. Not so for a small design..

 

[prady019]

The correct way is to write an HDL twstbench, but i am bound to use the same my project where i have VHDL Output File (.vho) available with me. Extension vho is a output of Quartus(Altera) simulator tool for FPGA. And only tcl is the way i find to test the design. Now i am in some progress with this but i still need to capture that value from data bus which is of output net type. Any suggestion ??

In the 2nd paragraph, what you have mention is design simu automation work. I hope you understand that both are completely different things.

I think both are ways to simulate your design. Difference is of either writing HDL testbench or providing TCL scripts. Correct me if i am wrong.

How would typing TCL into a command line ever be more convenient than typing into an HDL model? Regardless of design size, using TCL would probably only be better if you're fluent in TCL and an HDL throwback.

You are correct Kevin its not a convenient and i am not fluent in TCL but i am trying and you can help me.

Well, you can type it first and then copy them into a .do file and then run the .do file.....For a big design you will have to type a lot of commands. Not so for a small design..

I am not doing it via (.do) file because i am not sure how to do so. I have located (.vho) file in my project folder and simply run via double clicking. There i have command line interface of ModelSim where i paste TCL commands return in some different (.txt) file. And input/output signals can be observed over WAVE window.

 

[TrickyDicky]

a .do file is simply a tcl script.

From modelsim command window - type

do myfile.do

to execute the script, rather than copy/pasting each command manually.

I cannot find a command in the reference manual (installed under /<modelsim>/docs/) that will do what you want - you may be stuck having to write an HDL testbench after all.

 

[K-J]

The correct way is to write an HDL twstbench, but i am bound to use the same my project where i have VHDL Output File (.vho) available with me. Extension vho is a output of Quartus(Altera) simulator tool for FPGA. And only tcl is the way i find to test the design. Now i am in some progress with this but i still need to capture that value from data bus which is of output net type. Any suggestion ??

In addition to the .VHO file, you should also have the original source .VHD file. Get the testbench working with that first. Then substitute in the .VHO file. Both will have the same interface with the testbench so no changes should be needed to get the testbench working other than to fix issues with the testbench itself.

There is nothing to do to capture the outputs, they are already there. What you would do is check to see that they are correct with an assertion statement.

Kevin Jennings

 

[dpaul]

Hello prady019,

I think both are ways to simulate your design. Difference is of either writing HDL testbench or providing TCL scripts. Correct me if i am wrong.

In my last post I tried to isolate the two processes/steps for you so that you can grasp what needs to be done. But I think you are lacking some basic understanding here.

Now lets take a step backward. Do you have a testbench, a .vhd file with which you can provide stimulus to your DUT and can simulate your design (run for some us and see waveforms, etc)?

If yes, good, you have step-1 done. The next step would be the process of automatically running your testbench. That is done using a TCL script which will contain successive TCL commands bundled in a .do file. We can keep this aside currently; subjected to future discussion.

If not, then please develop a running test-bench first. TrickyDicky & K-J have already told you to do this in the last two posts. This is the first thing you must do.

I understand that simulating a big DUT repeatedly gets annoying over time and hence you want a TCL script to it. Yes, right approach. But I think the members (including me) are not sure if have a running test-bench!

 

[prady019]

do myfile.do to execute the script, rather than copy/pasting each command manually.

Thanks Tricky (.do) file is easy to handle. I am using the same for my TCL for now.:thumbsup:

In addition to the .VHO file, you should also have the original source .VHD file. Get the testbench working with that first. Then substitute in the .VHO file. Both will have the same interface with the testbench so no changes should be needed to get the testbench working other than to fix issues with the testbench itself.
There is nothing to do to capture the outputs, they are already there. What you would do is check to see that they are correct with an assertion statement.

Hello Kevin i am getting your point but i dont have orignal source code. That's the reason i am using TCL to varify the design, so i am trying to dump data bus output in a text file then observe the sequence and verify the design 8-O

Now lets take a step backward. Do you have a testbench, a .vhd file with which you can provide stimulus to your DUT and can simulate your design (run for some us and see waveforms, etc)?

If yes, good, you have step-1 done. The next step would be the process of automatically running your testbench. That is done using a TCL script which will contain successive TCL commands bundled in a .do file. We can keep this aside currently; subjected to future discussion.

If not, then please develop a running test-bench first. TrickyDicky & K-J have already told you to do this in the last two posts. This is the first thing you must do.

I understand that simulating a big DUT repeatedly gets annoying over time and hence you want a TCL script to it. Yes, right approach. But I think the members (including me) are not sure if have a running test-bench!

Hello Paul
1-step is the basics approach that i always follow, when i have source code written in HDL(Verilog or VHDL). But in this recent project, i don't have source code. Just the VHDL Output File (.vho) and few snapshots of block diagram.
And i understand that we use TCL for automating the process of simulation.
Whats the process name of 'writing TCL commands and monitoring ouput waveform on wave-window' if not simulation :?::?::?::?::?:

 

[ads-ee]

Hello Kevin i am getting your point but i dont have orignal source code. That's the reason i am using TCL to varify the design
1-step is the basics approach that i always follow, when i have source code written in HDL(Verilog or VHDL). But in this recent project, i don't have source code. Just the VHDL Output File (.vho) and few snapshots of block diagram.

Even if you don't have source code you can still write a testbench based on the interface specs. I'm not sure why you have a problem with that and insist on using a Tcl script to toggle the inputs of the DUT.

 

[prady019]

Even if you don't have source code you can still write a testbench based on the interface specs. I'm not sure why you have a problem with that and insist on using a Tcl script to toggle the inputs of the DUT.

Writing a testbench is not a problem. The problem is instantiating the top level in my testbench and then compile it. It can be easily done when i have source code but i don't know how to include my top_level_design which is already been compiled separately and i am left with VHDL Output File (.vho)

 

[dpaul]

I have never done it for a vho file, so I can't give you a conclusive answer.
But if I were you I would try out with whatever I have (ink. the vho files).
Have you tried it? Please refer to the *relevant* Vivado docu.

There *could be* some xilinx vivado commands that lets you achieve the above. The latter part would be putting all of these inside a TCL file.

 

[K-J]

Writing a testbench is not a problem. The problem is instantiating the top level in my testbench and then compile it. It can be easily done when i have source code but i don't know how to include my top_level_design which is already been compiled separately and i am left with VHDL Output File (.vho)

The .VHO file is VHDL source, you just compile it. Probably what you'll find is that you need to include various other device specific packages as well. These will be identified though as errors about unrecognized identifiers when you compile the .VHO file. So then you search the tool's directory to find the other files you need, compile them, compile the VHO file again. Repeat this process until the VHO file compiles without error.

However, what you're posting now that you don't know how to instantiate the top level conflicts completely with your original posting where you said "When i run the design after applying all the valid input to my DUT i can see change on my output net/reg". You can't possibly "see change on my output net/reg" if you didn't instantiate something, so it is not at all clear what in the world you have or what you were doing when you saw the DUT do something.

What any of this has to do with a TCL testbench is completely unclear. If you can't even describe what you are doing, then about all anyone here can do is wish you 'Good Luck'.

Kevin Jennings

 

[TrickyDicky]

Are you the same person as here:
https://www.alteraforum.com/forum/showthread.php?t=51132

 

[prady019]

Thank you guys for your help. Compiling the .vho and then simulating it with TCL was good idea but for just small piece of code. I took the advice from trickydicky and followed it. After lots of errors i have converted my code in .vhd code and now i am going to write the testbench for the same.
@tricky yes its me.