This code for Parity interlever in DVB-T2. I assign valuesusing case statement but which is also not going to synthesizing and taking long time.
case x is
when 32400 => index <= 32400 ;
when 32401 => index <= 32490 ;
when 32402 => index <= 32580 ;
when 32403 => index <= 32670 ;
when 32404 => index <= 32760 ;
when 32405 => index <= 32850 ;
.
.
.
.
.when 64799 => index <= 64799 ;
when others=> null;
end case;
These are about 32400 lines of case statements......
Im not ROM/RAM specialist but it should synthesize fast to ROM unless you made it as combinatorial statement (eg: process (x))
maybe pack it in process(CLK) statement so it will be synthesize correctly, or use vendor ROM declaration ?
or try declaration similar to
type array_ROM is array (0 to NUMBER_OF_ROWS-1) of std_logic_vector (ROM_BITWIDTH-1 downto 0);
As i recall i had no problems with this implementation. Maybe please attache with zip your code and post info on the software you are using for syntheze. (there maybe be problem that in syntcheze option u got marked do not use ROM/RAM and so on).
constant ROM : some_rom_array_t := (...a big list of values);
rom_process: process(clk)
begin
if rising_edge(clK) then
output <= ROM(addr);
end if;
end process;