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taking too lengthy time to synthesize

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win2010

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This code for Parity interlever in DVB-T2. I assign valuesusing case statement but which is also not going to synthesizing and taking long time.

case x is
when 32400 => index <= 32400 ;
when 32401 => index <= 32490 ;
when 32402 => index <= 32580 ;
when 32403 => index <= 32670 ;
when 32404 => index <= 32760 ;
when 32405 => index <= 32850 ;
.
.
.
.
.when 64799 => index <= 64799 ;
when others=> null;
end case;

These are about 32400 lines of case statements......

What is the solution for this ....?
 

Im not ROM/RAM specialist but it should synthesize fast to ROM unless you made it as combinatorial statement (eg: process (x))
maybe pack it in process(CLK) statement so it will be synthesize correctly, or use vendor ROM declaration ?

or try declaration similar to

type array_ROM is array (0 to NUMBER_OF_ROWS-1) of std_logic_vector (ROM_BITWIDTH-1 downto 0);

constant my_ROM : array_ROM
:=
(
x"FFFF",
.....
);

and pack it with process(CLK) f.e
 
Last edited:
ya, i made it also not synthesizing....
How to store these into RAM/ROM..?
 

As i recall i had no problems with this implementation. Maybe please attache with zip your code and post info on the software you are using for syntheze. (there maybe be problem that in syntcheze option u got marked do not use ROM/RAM and so on).
 
It will store to system ROM or it will become CLB...?
 

The constant approach is much easier to manage:

Code:
constant ROM : some_rom_array_t := (...a big list of values);

rom_process: process(clk)
begin
  if rising_edge(clK) then
    output <= ROM(addr);
  end if;
end process;
 
Is their any limit to use ROM because I`ve do it for very large values...?

means I need to store for 64800*8=518400
 

In spartan 6 single RAM is 18 Kb memory array.
 

my question is if I use ARRAY in " spartan-3A DSP" program which uses ROM/RAM or CLB/FlipFlops......?

type array_ROM is array (0 to 64799) of integer;
constant index : array_ROM:= (a list of values.........);
 

it depends on how you use the array. If you follow the coding guidlines from Xilinx, you should be able to use the RAMs.
 

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